Design of a Voltage-controlled Ring Oscillator Using Cascode Voltage Switch Logic with Data Anticipation in 0.18[mu]m CMOS PDF Download
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Author: Satmandir Kaur Khalsa Publisher: ISBN: Category : Languages : en Pages : 60
Book Description
To design for high performance circuits, a precision clock with low jitter is needed to meet the high frequency requirements. A phase-locked loop (PLL) is used to achieve the required low jitter. The phase-locked loop architecture can be simplified down to a few major blocks: a phase detector, a loop filter, a voltage-controlled oscillator, and a frequency divider. The voltage-controlled oscillator (VCO) which is the subject of this report uses a ring oscillator that incorporates delay cells using cascode voltage switch logic with data anticipation in the differential inverter design. The data anticipation is achieved by using two PMOS pull up transistors that are controlled by the previous delay cell, thereby increasing the switching speed of the ring oscillator. The cascode voltage switch logic uses complementary signals to minimize jitter. The frequency of the oscillator is controlled by varying the VCO supply voltage, which gives a wide range of frequencies.
Author: Satmandir Kaur Khalsa Publisher: ISBN: Category : Languages : en Pages : 60
Book Description
To design for high performance circuits, a precision clock with low jitter is needed to meet the high frequency requirements. A phase-locked loop (PLL) is used to achieve the required low jitter. The phase-locked loop architecture can be simplified down to a few major blocks: a phase detector, a loop filter, a voltage-controlled oscillator, and a frequency divider. The voltage-controlled oscillator (VCO) which is the subject of this report uses a ring oscillator that incorporates delay cells using cascode voltage switch logic with data anticipation in the differential inverter design. The data anticipation is achieved by using two PMOS pull up transistors that are controlled by the previous delay cell, thereby increasing the switching speed of the ring oscillator. The cascode voltage switch logic uses complementary signals to minimize jitter. The frequency of the oscillator is controlled by varying the VCO supply voltage, which gives a wide range of frequencies.
Author: Liang Dai Publisher: Springer Science & Business Media ISBN: 1461511453 Category : Technology & Engineering Languages : en Pages : 170
Book Description
Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results. The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.
Author: Fatemeh Taghizadehmarvast Publisher: LAP Lambert Academic Publishing ISBN: 9783659357022 Category : Languages : en Pages : 116
Book Description
This thesis is presented 10 GHz voltage controlled ring oscillator for high speed application. The voltage controlled ring oscillator was designed and fabricated in 0.13 m CMOS technology. The oscillator is a 7-stages ring oscillator with one inverter that replaced by NAND-gate for shutting down in the ring oscillator during idle mode. seven-state inverter was used to control the 126 bit vector in ring oscillator. the transistor sizing was used to improve performance of the ring oscillator in PLL. In this project, layout of ring oscillator was designed and optimized as small as possible to be using L-EDIT software. The predicated performance is verified by analyses and simulation using H-spice and L-EDIT tools. This ring oscillator is optimized to compare with earlier design. The ring oscillator can operate with 1.8v supply voltage .
Author: Sushil Kumar Publisher: LAP Lambert Academic Publishing ISBN: 9783659551574 Category : Languages : en Pages : 116
Book Description
In the tremendous growth of wireless handheld devices, low power consumption becomes a major consideration in radio frequency integrated circuit (RFIC) designs. This book introduces a multistage voltage controlled ring oscillator. The proposed structure uses 45 nm CMOS Technology in cadence. PSS analyses are performed in order to determine the frequency of oscillation and the influence of parameters such as supply voltage, temperature or load capacitance over the oscillation frequency. A transient analysis is performed to illustrate the effects of the parasitic parameters over the oscillation frequency. Ring oscillators with different number of stages like 7, 9 and 11 were designed successfully and their performance parameters are discussed in great detail and compared to reach to solutions to the challenges faced by the current Ring Oscillator technology. The challenges are phase noise, frequency jitter, period jitter, delay, jitter, total harmonic distortion (THD), transfer function etc. and are dealt appropriately in the system designs proposed for different number of stages. For example, a certain signal may have a phase noise of -80 dBc/Hz at an offset of 10 KHz.
Author: Suman Shruti Publisher: LAP Lambert Academic Publishing ISBN: 9783659748677 Category : Languages : en Pages : 84
Book Description
A voltage controlled ring oscillator plays very important role in high speed systems due to its easy integration capability. The analysis of different VCOs and their applications are discussed and analyzed in this book. There are number of applications of ring VCOs, one of the most important application is phase locked loop. The main task of the PLL is to maintain the coherence between output signal and reference signal by phase comparison. The proposed PLL using improved performance voltage controlled ring oscillator shows better performance in terms of frequency range and power consumption.
Author: John A. McNeill Publisher: Springer Science & Business Media ISBN: 038776528X Category : Technology & Engineering Languages : en Pages : 292
Book Description
This guide emphasizes jitter for time domain applications so that there is not a need to translate from frequency domain. This provides a more direct path to the results for designing in an application area where performance is specified in the time domain. The book includes classification of oscillator types and an exhaustive guide to existing research literature. It also includes classification of measurement techniques to help designers understand how the eventual performance of circuit design is verified.
Author: Rohit Yadav Publisher: ISBN: Category : Languages : en Pages : 204
Book Description
In advanced short-channel CMOS processes, analog circuit-design poses significant challenges imposed by the low power-supply voltage, and the reduced intrinsic-gain of short channel-effects of CMOS-transistors. However, continued scaling of CMOS devices makes them faster and thus enables the design of high-speed circuits such as oscillators at lower power-levels. Voltage and current-controlled oscillators are essential building blocks for designing Delta-Sigma analog-to-digital converters (ADC) that do not require a sample and hold circuits up front. This research focuses on designing scaling-friendly, linear, low-power CMOS relaxation-oscillators for Delta-Sigma analog to digital conversion. Ring oscillators using an odd number of digital-inverters provide a simple reliable-solution, and thus are popular. So the first approach is to increase the speed (time-resolution) by simply lowering the inverter-gain using the translinear and temperature-invariant voltage-mirror circuits instead of open-loop inverters. Here two scaled-inverters are used to obtain gain exploiting the function and its functional inverse idea to obtain the required loop-gain. Here we are simply trading gain to increase speed at the expense of power. An alternative approach is to use the gyrator circuit to emulate an inductor. Two transconductors with opposite polarity current-output are needed to form a gyrator. Inverting the output-polarity is achieved using a translinear, unity-gain current-mirror achieving stability of the gyrator circuit that uses negative feedback. Using these, an LC -coupled ring-oscillator is emulated. These provide a more robust solution. Process, supply-voltage and temperature (PVT) variations are traditionally minimized by the well-established technique of negative-feedback in circuits using Bandgap reference voltage and passive elements like MIM capacitors. Thus the design of an operational current to frequency converter (OCFC) is proposed. This is inspired by the success of the notion of an operational amplifier (OPAMP) that has a very large gain. It is always configured to trade gain for obtaining linearity using negative- feedback making the feedback network set the precision of the transfer function. The OCFC uses the same idea using a switched-capacitor linear frequency-to-current detector in the feedback path to make the closed-loop tuning-curve linear, having a low temperature-coefficient. The design of a simple linear oscillator based on a traditional multivibrator-circuit is explored for two specific applications. There is a need for a medium-resolution low-speed 10-bit ADC for IOT applications. The other is for a 6-bit converter for high-speed data-communication systems. The idea is to obtain the performance requirements with no need for power-hungry digital-calibration. Manufacturability, and cost are the prime focus here. Finally, an open loop Delta-Sigma modulator designed using pseudo-differential ring oscillators is explored for low bandwidth and medium resolution analog-to-digital conversion applications. It employs a nonlinearity cancellation technique in the voltage-to-current (V/I) converter to improve resolution. Most of the circuit can be synthesized using digital toolchain except for the front-end V/I converter to reduce turn-around time. All the circuits presented in this thesis are verified at multiple process nodes ranging from 180nm to 22nm. The simulation-results presented here are mostly using the models for the 180nm TSMC process
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Author: Satmandir Kaur Khalsa![Design of a Voltage-controlled Ring Oscillator Using Cascode Voltage Switch Logic with Data Anticipation in 0.18[mu]m CMOS PDF](https://books.google.com/books/content/images/frontcover/fzS1swEACAAJ?fife=w80-h100)
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