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Author: Yongquan Fan Publisher: Springer Science & Business Media ISBN: 9048193982 Category : Technology & Engineering Languages : en Pages : 200
Book Description
High-Speed Serial Interface (HSSI) devices have become widespread in communications, from the embedded to high-performance computing systems, and from on-chip to a wide haul. Testing of HSSIs has been a challenging topic because of signal integrity issues, long test time and the need of expensive instruments. Accelerating Test, Validation and Debug of High Speed Serial Interfaces provides innovative test and debug approaches and detailed instructions on how to arrive to practical test of modern high-speed interfaces. Accelerating Test, Validation and Debug of High Speed Serial Interfaces first proposes a new algorithm that enables us to perform receiver test more than 1000 times faster. Then an under-sampling based transmitter test scheme is presented. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100ms, while the test usually takes seconds. The book also presents and external loopback-based testing scheme, where and FPGA-based BER tester and a novel jitter injection technique are proposed. These schemes can be applied to validate, test and debug HSSIs with data rate up to 12.5Gbps at a lower test cost than pure ATE solutions. In addition, the book introduces an efficieng scheme to implement high performance Gaussian noise generators, suitable for evaluating BER performance under noise conditions.
Author: Yongquan Fan Publisher: Springer Science & Business Media ISBN: 9048193982 Category : Technology & Engineering Languages : en Pages : 200
Book Description
High-Speed Serial Interface (HSSI) devices have become widespread in communications, from the embedded to high-performance computing systems, and from on-chip to a wide haul. Testing of HSSIs has been a challenging topic because of signal integrity issues, long test time and the need of expensive instruments. Accelerating Test, Validation and Debug of High Speed Serial Interfaces provides innovative test and debug approaches and detailed instructions on how to arrive to practical test of modern high-speed interfaces. Accelerating Test, Validation and Debug of High Speed Serial Interfaces first proposes a new algorithm that enables us to perform receiver test more than 1000 times faster. Then an under-sampling based transmitter test scheme is presented. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100ms, while the test usually takes seconds. The book also presents and external loopback-based testing scheme, where and FPGA-based BER tester and a novel jitter injection technique are proposed. These schemes can be applied to validate, test and debug HSSIs with data rate up to 12.5Gbps at a lower test cost than pure ATE solutions. In addition, the book introduces an efficieng scheme to implement high performance Gaussian noise generators, suitable for evaluating BER performance under noise conditions.
Author: Cecilia Gimeno Gasca Publisher: Springer ISBN: 3319105639 Category : Technology & Engineering Languages : en Pages : 164
Book Description
This book introduces readers to the design of adaptive equalization solutions integrated in standard CMOS technology for high-speed serial links. Since continuous-time equalizers offer various advantages as an alternative to discrete-time equalizers at multi-gigabit rates, this book provides a detailed description of continuous-time adaptive equalizers design - both at transistor and system levels-, their main characteristics and performances. The authors begin with a complete review and analysis of the state of the art of equalizers for wireline applications, describing why they are necessary, their types, and their main applications. Next, theoretical fundamentals of continuous-time adaptive equalizers are explored. Then, new structures are proposed to implement the different building blocks of the adaptive equalizer: line equalizer, loop-filters, power comparator, etc. The authors demonstrate the design of a complete low-power, low-voltage, high-speed, continuous-time adaptive equalizer. Finally, a cost-effective CMOS receiver which includes the proposed continuous-time adaptive equalizer is designed for 1.25 Gb/s optical communications through 50-m length, 1-mm diameter plastic optical fiber (POF).
Author: Hanqiao Zhang Publisher: Elsevier ISBN: 012418667X Category : Technology & Engineering Languages : en Pages : 268
Book Description
High Speed Digital Design discusses the major factors to consider in designing a high speed digital system and how design concepts affect the functionality of the system as a whole. It will help you understand why signals act so differently on a high speed digital system, identify the various problems that may occur in the design, and research solutions to minimize their impact and address their root causes. The authors offer a strong foundation that will help you get high speed digital system designs right the first time. Taking a systems design approach, High Speed Digital Design offers a progression from fundamental to advanced concepts, starting with transmission line theory, covering core concepts as well as recent developments. It then covers the challenges of signal and power integrity, offers guidelines for channel modeling, and optimizing link circuits. Tying together concepts presented throughout the book, the authors present Intel processors and chipsets as real-world design examples. - Provides knowledge and guidance in the design of high speed digital circuits - Explores the latest developments in system design - Covers everything that encompasses a successful printed circuit board (PCB) product - Offers insight from Intel insiders about real-world high speed digital design
Author: Slawomir Koziel Publisher: World Scientific ISBN: 1800610769 Category : Technology & Engineering Languages : en Pages : 467
Book Description
Contemporary high-frequency engineering design heavily relies on full-wave electromagnetic (EM) analysis. This is primarily due to its versatility and ability to account for phenomena that are important from the point of view of system performance. Unfortunately, versatility comes at the price of a high computational cost of accurate evaluation. Consequently, utilization of simulation models in the design processes is challenging although highly desirable. The aforementioned problems can be alleviated by means of surrogate modeling techniques, the most popular of which are data-driven models. Although a large variety of methods are available, they are all affected by the curse of dimensionality. This is especially pronounced in high-frequency electronics, where typical system responses are highly nonlinear. Construction of practically useful surrogates covering wide ranges of parameters and operating conditions is a considerable challenge.Surrogate Modeling for High-Frequency Design presents a selection of works representing recent advancements in surrogate modeling and their applications to high-frequency design. Some chapters provide a review of specific topics such as neural network modeling of microwave components, while others describe recent attempts to improve existing modeling methodologies. Furthermore, the book features numerous applications of surrogate modeling methodologies to design optimization and uncertainty quantification of antenna, microwave, and analog RF circuits.
Author: Laung-Terng Wang Publisher: Morgan Kaufmann ISBN: 0080556809 Category : Technology & Engineering Languages : en Pages : 893
Book Description
Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. - Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. - Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. - Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. - Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. - Practical problems at the end of each chapter for students.
Author: Vazgen Melikyan Publisher: Springer Nature ISBN: 3031507142 Category : Technology & Engineering Languages : en Pages : 351
Book Description
This book describes machine learning-based new principles, methods of design and optimization of high-speed integrated circuits, included in one electronic system, which can exchange information between each other up to 128/256/512 Gbps speed. The efficiency of methods has been proven and is described on the examples of practical designs. This will enable readers to use them in similar electronic system designs. The author demonstrates newly developed principles and methods to accelerate communication between ICs, working in non-standard operating conditions, considering signal deviation compensation with linearity self-calibration. The observed circuit types also include but are not limited to mixed-signal, high performance heterogeneous integrated circuits as well as digital cores.
Author: Shuvra S. Bhattacharyya Publisher: Springer Science & Business Media ISBN: 1461468590 Category : Technology & Engineering Languages : en Pages : 1395
Book Description
Handbook of Signal Processing Systems is organized in three parts. The first part motivates representative applications that drive and apply state-of-the art methods for design and implementation of signal processing systems; the second part discusses architectures for implementing these applications; the third part focuses on compilers and simulation tools, describes models of computation and their associated design tools and methodologies. This handbook is an essential tool for professionals in many fields and researchers of all levels.
Author: Yongquan Fan
Author: Yongquan Fan
Author: Cecilia Gimeno Gasca
Author: Hanqiao Zhang
Author: Slawomir Koziel
Author: 
Author: 
Author: Laung-Terng Wang
Author: 
Author: Vazgen Melikyan
Author: Shuvra S. Bhattacharyya