Compact Modeling of Quantum Effects in Double Gate MOSFETs PDF Download

Author: Wei Wang
Publisher:
ISBN: 9781109906974
Category :
Languages : en
Pages : 145

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Book Description
As CMOS scales down to the limits imposed by oxide tunneling and voltage non-scaling, double-gate (DG) MOSFET has become a subject of intense VLSI research. In this dissertation, quantum effects were investigated in both long channel and short channel Double-Gate MOSFETs.

Author: Huaxin Lu
Publisher:
ISBN:
Category :
Languages : en
Pages : 143

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Book Description
Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects. Currently, much research effort is devoted to the development of DG MOSFETs. This dissertation focuses on the compact modeling of DG MOSFETs, aiming to extract the physics of DG MOSFETs and provide a tool for simulating DG MOSFET circuits. We start from the basic Poisson's equation and current continuity equation to rigorously derive the long-channel drain current model without the charge sheet approximation. The model is based on an analytical solution to the potential distribution at any point in the DG MOSFET. It employs one single equation to cover all the operation regions: linear, saturation, and subthreshold, continuously with no fitting parameter. Volume inversion, a non-charge-sheet phenomenon in symmetric DG MOSFETs, is accurately captured by the model. For AC and transient simulations, analytical charge and capacitance models are developed. Both symmetric and asymmetric DG MOSFET models are verified by extensive two dimensional numerical simulations. For small-geometry devices, compact models of the physical phenomena such as short channel effects are developed. In the development of the compact models, special attention is paid to ensure the model is symmetric and continuous in all the operation regions. Quantum effect is also incorporated in the long channel core model. As body doping may be needed to adjust the threshold voltage, we also studied the body doping effect on DG MOSFET and concluded that lightly doped DG MOSFETs can be modeled by adding a threshold voltage shift to the undoped DG MOSFET model. The model has been implemented into SPICE3 and Verilog-A platforms so that it can be used by circuit designers. In the implementation, Newton method is used for solving an implicit equation in the calculation of drain current. We also calibrated the model with respect to the published hardware data to affirm its consistency with the experimental I-V curves. Finally, the model has been released in public domain http://taur.ucsd.edu/~hlu for circuit simulation.

Author: Amara Amara
Publisher: Springer Science & Business Media
ISBN: 1402093411
Category : Technology & Engineering
Languages : en
Pages : 215

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Book Description
Until the 1990s, the reduction of the minimum feature sizes used to fabricate in- grated circuits, called “scaling”, has highlighted serious advantages as integration density, speed, power consumption, functionality and cost. Direct consequence was the decrease of cost-per-function, so the electronic productivity has largely progressed in this period. Another usually cited trend is the evolution of the in- gration density as expressed by the well-know Moore’s Law in 1975: the number of devices per chip doubles every 2 years. This evolution has allowed improving signi?cantly the circuit complexity, offering a great computing power in the case of microprocessor, for example. However, since few years, signi?cant issues appeared such as the increase of the circuit heating, device complexity, variability and dif?culties to improve the integration density. These new trends generate an important growth in development and production costs. Though is it, since 40 years, the evolution of the microelectronics always f- lowed the Moore’s law and each dif?culty has found a solution.

Author: Farzan Jazaeri
Publisher: Cambridge University Press
ISBN: 1108581390
Category : Technology & Engineering
Languages : en
Pages : 255

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Book Description
The first book on the topic, this is a comprehensive introduction to the modeling and design of junctionless field effect transistors (FETs). Beginning with a discussion of the advantages and limitations of the technology, the authors also provide a thorough overview of published analytical models for double-gate and nanowire configurations, before offering a general introduction to the EPFL charge-based model of junctionless FETs. Important features are introduced gradually, including nanowire versus double-gate equivalence, technological design space, junctionless FET performances, short channel effects, transcapacitances, asymmetric operation, thermal noise, interface traps, and the junction FET. Additional features compatible with biosensor applications are also discussed. This is a valuable resource for students and researchers looking to understand more about this new and fast developing field.

Author: Samar K. Saha
Publisher: CRC Press
ISBN: 148224067X
Category : Technology & Engineering
Languages : en
Pages : 548

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Book Description
Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond provides a modern treatise on compact models for circuit computer-aided design (CAD). Written by an author with more than 25 years of industry experience in semiconductor processes, devices, and circuit CAD, and more than 10 years of academic experience in teaching compact modeling courses, this first-of-its-kind book on compact SPICE models for very-large-scale-integrated (VLSI) chip design offers a balanced presentation of compact modeling crucial for addressing current modeling challenges and understanding new models for emerging devices. Starting from basic semiconductor physics and covering state-of-the-art device regimes from conventional micron to nanometer, this text: Presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models Discusses the major issue of process variability, which severely impacts device and circuit performance in advanced technologies and requires statistical compact models Promotes further research of the evolution and development of compact models for VLSI circuit design and analysis Supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices Includes exercise problems at the end of each chapter and extensive references at the end of the book Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond is intended for senior undergraduate and graduate courses in electrical and electronics engineering as well as for researchers and practitioners working in the area of electron devices. However, even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts from this book.

Author: Gennady Gildenblat
Publisher: Springer Science & Business Media
ISBN: 9048186145
Category : Technology & Engineering
Languages : en
Pages : 531

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Book Description
Most of the recent texts on compact modeling are limited to a particular class of semiconductor devices and do not provide comprehensive coverage of the field. Having a single comprehensive reference for the compact models of most commonly used semiconductor devices (both active and passive) represents a significant advantage for the reader. Indeed, several kinds of semiconductor devices are routinely encountered in a single IC design or in a single modeling support group. Compact Modeling includes mostly the material that after several years of IC design applications has been found both theoretically sound and practically significant. Assigning the individual chapters to the groups responsible for the definitive work on the subject assures the highest possible degree of expertise on each of the covered models.

Author: Gajanan Dessai
Publisher:
ISBN:
Category : Field-effect transistors
Languages : en
Pages : 126

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Book Description
Scaling of the classical planar MOSFET below 20 nm gate length is facing not only technological difficulties but also limitations imposed by short channel effects, gate and junction leakage current due to quantum tunneling, high body doping induced threshold voltage variation, and carrier mobility degradation. Non-classical multiple-gate structures such as double-gate (DG) FinFETs and surrounding gate field-effect-transistors (SGFETs) have good electrostatic integrity and are an alternative to planar MOSFETs for below 20 nm technology nodes. Circuit design with these devices need compact models for SPICE simulation. In this work physics based compact models for the common-gate symmetric DG-FinFET, independent-gate asymmetric DG-FinFET, and SGFET are developed. Despite the complex device structure and boundary conditions for the Poisson-Boltzmann equation, the core structure of the DG-FinFET and SGFET models, are maintained similar to the surface potential based compact models for planar MOSFETs such as SP and PSP. TCAD simulations show differences between the transient behavior and the capacitance-voltage characteristics of bulk and SOI FinFETs if the gate-voltage swing includes the accumulation region. This effect can be captured by a compact model of FinFETs only if it includes the contribution of both types of carriers in the Poisson-Boltzmann equation. An accurate implicit input voltage equation valid in all regions of operation is proposed for common-gate symmetric DG-FinFETs with intrinsic or lightly doped bodies. A closed-form algorithm is developed for solving the new input voltage equation including ambipolar effects. The algorithm is verified for both the surface potential and its derivatives and includes a previously published analytical approximation for surface potential as a special case when ambipolar effects can be neglected. The symmetric linearization method for common-gate symmetric DG-FinFETs is developed in a form free of the charge-sheet approximation present in its original formulation for bulk MOSFETs. The accuracy of the proposed technique is verified by comparison with exact results. An alternative and computationally efficient description of the boundary between the trigonometric and hyperbolic solutions of the Poisson-Boltzmann equation for the independent-gate asymmetric DG-FinFET is developed in terms of the Lambert W function. Efficient numerical algorithm is proposed for solving the input voltage equation. Analytical expressions for terminal charges of an independent-gate asymmetric DG-FinFET are derived. The new charge model is C-infinity continuous, valid for weak as well as for strong inversion condition of both the channels and does not involve the charge-sheet approximation. This is accomplished by developing the symmetric linearization method in a form that does not require identical boundary conditions at the two Si-SiO2 interfaces and allows for volume inversion in the DG-FinFET. Verification of the model is performed with both numerical computations and 2D TCAD simulations under a wide range of biasing conditions. The model is implemented in a standard circuit simulator through Verilog-A code. Simulation examples for both digital and analog circuits verify good model convergence and demonstrate the capabilities of new circuit topologies that can be implemented using independent-gate asymmetric DG-FinFETs.

Author: Angsuman Sarkar
Publisher: CRC Press
ISBN: 1000565394
Category : Science
Languages : en
Pages : 377

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Book Description
Providing cutting-edge research on nanoelectronics and photonic devices and its application in future integrated circuits, this state-of-the-art book tackles the challenges of the different detailed theoretical and analytical models of solving the problems of various nanodevices. The volume also explores from different angles the roles of material composition and choice of materials that now play the most critical role in determining outcomes of low-dimensional nanoelectronic devices. The applications of those findings are extremely beneficial for the computing and telecommunication industries. Beginning with a solid theoretical background for every chapter, this volume covers the hottest areas of present-day electronic engineering. The continuous miniaturization of devices, components, and systems requires corresponding cutting-edge theoretical analysis supported by simulated findings before actual fabrication. That purpose is given maximum focus in this volume, which has interdisciplinary appeal, making it a comprehensive technological volume that deals with underlying aspects of physics, materials, structures in nano-regime, and the corresponding end-product in the form of devices.

Author: Sorin Alexander Huss
Publisher: Springer Science & Business Media
ISBN: 1402061498
Category : Technology & Engineering
Languages : en
Pages : 352

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Book Description
This book is the latest contribution to the Chip Design Languages series and it consists of selected papers presented at the Forum on Specifications and Design Languages (FDL'06), in September 2006. The book represents the state-of-the-art in research and practice, and it identifies new research directions. It highlights the role of specification and modelling languages, and presents practical experiences with specification and modelling languages.

Author: Shubham Sahay
Publisher: John Wiley & Sons
ISBN: 1119523524
Category : Technology & Engineering
Languages : en
Pages : 619

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Book Description
A comprehensive one-volume reference on current JLFET methods, techniques, and research Advancements in transistor technology have driven the modern smart-device revolution—many cell phones, watches, home appliances, and numerous other devices of everyday usage now surpass the performance of the room-filling supercomputers of the past. Electronic devices are continuing to become more mobile, powerful, and versatile in this era of internet-of-things (IoT) due in large part to the scaling of metal-oxide semiconductor field-effect transistors (MOSFETs). Incessant scaling of the conventional MOSFETs to cater to consumer needs without incurring performance degradation requires costly and complex fabrication process owing to the presence of metallurgical junctions. Unlike conventional MOSFETs, junctionless field-effect transistors (JLFETs) contain no metallurgical junctions, so they are simpler to process and less costly to manufacture.JLFETs utilize a gated semiconductor film to control its resistance and the current flowing through it. Junctionless Field-Effect Transistors: Design, Modeling, and Simulation is an inclusive, one-stop referenceon the study and research on JLFETs This timely book covers the fundamental physics underlying JLFET operation, emerging architectures, modeling and simulation methods, comparative analyses of JLFET performance metrics, and several other interesting facts related to JLFETs. A calibrated simulation framework, including guidance on SentaurusTCAD software, enables researchers to investigate JLFETs, develop new architectures, and improve performance. This valuable resource: Addresses the design and architecture challenges faced by JLFET as a replacement for MOSFET Examines various approaches for analytical and compact modeling of JLFETs in circuit design and simulation Explains how to use Technology Computer-Aided Design software (TCAD) to produce numerical simulations of JLFETs Suggests research directions and potential applications of JLFETs Junctionless Field-Effect Transistors: Design, Modeling, and Simulation is an essential resource for CMOS device design researchers and advanced students in the field of physics and semiconductor devices.