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Author: Gajanan Dessai Publisher: ISBN: Category : Field-effect transistors Languages : en Pages : 126
Book Description
Scaling of the classical planar MOSFET below 20 nm gate length is facing not only technological difficulties but also limitations imposed by short channel effects, gate and junction leakage current due to quantum tunneling, high body doping induced threshold voltage variation, and carrier mobility degradation. Non-classical multiple-gate structures such as double-gate (DG) FinFETs and surrounding gate field-effect-transistors (SGFETs) have good electrostatic integrity and are an alternative to planar MOSFETs for below 20 nm technology nodes. Circuit design with these devices need compact models for SPICE simulation. In this work physics based compact models for the common-gate symmetric DG-FinFET, independent-gate asymmetric DG-FinFET, and SGFET are developed. Despite the complex device structure and boundary conditions for the Poisson-Boltzmann equation, the core structure of the DG-FinFET and SGFET models, are maintained similar to the surface potential based compact models for planar MOSFETs such as SP and PSP. TCAD simulations show differences between the transient behavior and the capacitance-voltage characteristics of bulk and SOI FinFETs if the gate-voltage swing includes the accumulation region. This effect can be captured by a compact model of FinFETs only if it includes the contribution of both types of carriers in the Poisson-Boltzmann equation. An accurate implicit input voltage equation valid in all regions of operation is proposed for common-gate symmetric DG-FinFETs with intrinsic or lightly doped bodies. A closed-form algorithm is developed for solving the new input voltage equation including ambipolar effects. The algorithm is verified for both the surface potential and its derivatives and includes a previously published analytical approximation for surface potential as a special case when ambipolar effects can be neglected. The symmetric linearization method for common-gate symmetric DG-FinFETs is developed in a form free of the charge-sheet approximation present in its original formulation for bulk MOSFETs. The accuracy of the proposed technique is verified by comparison with exact results. An alternative and computationally efficient description of the boundary between the trigonometric and hyperbolic solutions of the Poisson-Boltzmann equation for the independent-gate asymmetric DG-FinFET is developed in terms of the Lambert W function. Efficient numerical algorithm is proposed for solving the input voltage equation. Analytical expressions for terminal charges of an independent-gate asymmetric DG-FinFET are derived. The new charge model is C-infinity continuous, valid for weak as well as for strong inversion condition of both the channels and does not involve the charge-sheet approximation. This is accomplished by developing the symmetric linearization method in a form that does not require identical boundary conditions at the two Si-SiO2 interfaces and allows for volume inversion in the DG-FinFET. Verification of the model is performed with both numerical computations and 2D TCAD simulations under a wide range of biasing conditions. The model is implemented in a standard circuit simulator through Verilog-A code. Simulation examples for both digital and analog circuits verify good model convergence and demonstrate the capabilities of new circuit topologies that can be implemented using independent-gate asymmetric DG-FinFETs.
Author: Gajanan Dessai Publisher: ISBN: Category : Field-effect transistors Languages : en Pages : 126
Book Description
Scaling of the classical planar MOSFET below 20 nm gate length is facing not only technological difficulties but also limitations imposed by short channel effects, gate and junction leakage current due to quantum tunneling, high body doping induced threshold voltage variation, and carrier mobility degradation. Non-classical multiple-gate structures such as double-gate (DG) FinFETs and surrounding gate field-effect-transistors (SGFETs) have good electrostatic integrity and are an alternative to planar MOSFETs for below 20 nm technology nodes. Circuit design with these devices need compact models for SPICE simulation. In this work physics based compact models for the common-gate symmetric DG-FinFET, independent-gate asymmetric DG-FinFET, and SGFET are developed. Despite the complex device structure and boundary conditions for the Poisson-Boltzmann equation, the core structure of the DG-FinFET and SGFET models, are maintained similar to the surface potential based compact models for planar MOSFETs such as SP and PSP. TCAD simulations show differences between the transient behavior and the capacitance-voltage characteristics of bulk and SOI FinFETs if the gate-voltage swing includes the accumulation region. This effect can be captured by a compact model of FinFETs only if it includes the contribution of both types of carriers in the Poisson-Boltzmann equation. An accurate implicit input voltage equation valid in all regions of operation is proposed for common-gate symmetric DG-FinFETs with intrinsic or lightly doped bodies. A closed-form algorithm is developed for solving the new input voltage equation including ambipolar effects. The algorithm is verified for both the surface potential and its derivatives and includes a previously published analytical approximation for surface potential as a special case when ambipolar effects can be neglected. The symmetric linearization method for common-gate symmetric DG-FinFETs is developed in a form free of the charge-sheet approximation present in its original formulation for bulk MOSFETs. The accuracy of the proposed technique is verified by comparison with exact results. An alternative and computationally efficient description of the boundary between the trigonometric and hyperbolic solutions of the Poisson-Boltzmann equation for the independent-gate asymmetric DG-FinFET is developed in terms of the Lambert W function. Efficient numerical algorithm is proposed for solving the input voltage equation. Analytical expressions for terminal charges of an independent-gate asymmetric DG-FinFET are derived. The new charge model is C-infinity continuous, valid for weak as well as for strong inversion condition of both the channels and does not involve the charge-sheet approximation. This is accomplished by developing the symmetric linearization method in a form that does not require identical boundary conditions at the two Si-SiO2 interfaces and allows for volume inversion in the DG-FinFET. Verification of the model is performed with both numerical computations and 2D TCAD simulations under a wide range of biasing conditions. The model is implemented in a standard circuit simulator through Verilog-A code. Simulation examples for both digital and analog circuits verify good model convergence and demonstrate the capabilities of new circuit topologies that can be implemented using independent-gate asymmetric DG-FinFETs.
Author: J.-P. Colinge Publisher: Springer Science & Business Media ISBN: 038771751X Category : Technology & Engineering Languages : en Pages : 350
Book Description
This book explains the physics and properties of multi-gate field-effect transistors (MuGFETs), how they are made and how circuit designers can use them to improve the performances of integrated circuits. It covers the emergence of quantum effects due to the reduced size of the devices and describes the evolution of the MOS transistor from classical structures to SOI (silicon-on-insulator) and then to MuGFETs.
Author: Matthew Thomas Donizetti Publisher: ISBN: Category : Metal oxide semiconductor field-effect transistors Languages : en Pages : 0
Book Description
With the advent of multi gate and nanoscale fabrication techniques, several new transistor topographies have been proposed and manufactured in the past decade. In parallel, accurate and efficient compact models for these devices have been likewise developed. This paper summarizes the major topographies and their associated compact models with a focus toward computationally efficient models constructed for implementation in common modeling languages such as Verilog-A and SPICE. Common physical and mathematical modeling techniques have also been reviewed as has the evolution from simple multi gate devices to nanoscale structures.
Author: Yogesh Singh Chauhan Publisher: Elsevier ISBN: 0323958230 Category : Technology & Engineering Languages : en Pages : 326
Book Description
FinFET/GAA Modeling for IC Simulation and Design: Using the BSIM-CMG Standard, Second Edition is the first to book to explain FinFET modeling for IC simulation and the industry standard – BSIM-CMG - describing the rush in demand for advancing the technology from planar to 3D architecture as now enabled by the approved industry standard. The book gives a strong foundation on the physics and operation of FinFET, details aspects of the BSIM-CMG model such as surface potential, charge and current calculations, and includes a dedicated chapter on parameter extraction procedures, thus providing a step-by-step approach for the efficient extraction of model parameters. With this book, users will learn Why you should use FinFET, The physics and operation of FinFET Details of the FinFET standard model (BSIM-CMG), Parameter extraction in BSIM-CMG FinFET circuit design and simulation, and more. - Authored by the lead inventor and developer of FinFET and developers of the BSIM-CMG standard model, providing an expert's insight into the specifications of the standard - A new edition of the original groundbreaking book on the industry-standard FinFET model—BSIM-CMGNew to This Edition - Includes a new chapter providing a comprehensive introduction to GAAFET, including motivations, device concepts, structure, benefits, and the industry standard GAAFET model - Covers the most recent developments in the BSIM-CMG model - Presents an updated RF modeling of FinFET using the BSIM-CMG model including parameter extraction - Includes a new chapter on cryogenic modeling
Author: Gennady Gildenblat Publisher: Springer Science & Business Media ISBN: 9048186145 Category : Technology & Engineering Languages : en Pages : 531
Book Description
Most of the recent texts on compact modeling are limited to a particular class of semiconductor devices and do not provide comprehensive coverage of the field. Having a single comprehensive reference for the compact models of most commonly used semiconductor devices (both active and passive) represents a significant advantage for the reader. Indeed, several kinds of semiconductor devices are routinely encountered in a single IC design or in a single modeling support group. Compact Modeling includes mostly the material that after several years of IC design applications has been found both theoretically sound and practically significant. Assigning the individual chapters to the groups responsible for the definitive work on the subject assures the highest possible degree of expertise on each of the covered models.
Author: Samar K. Saha Publisher: CRC Press ISBN: 1351831070 Category : Technology & Engineering Languages : en Pages : 385
Book Description
Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond provides a modern treatise on compact models for circuit computer-aided design (CAD). Written by an author with more than 25 years of industry experience in semiconductor processes, devices, and circuit CAD, and more than 10 years of academic experience in teaching compact modeling courses, this first-of-its-kind book on compact SPICE models for very-large-scale-integrated (VLSI) chip design offers a balanced presentation of compact modeling crucial for addressing current modeling challenges and understanding new models for emerging devices. Starting from basic semiconductor physics and covering state-of-the-art device regimes from conventional micron to nanometer, this text: Presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models Discusses the major issue of process variability, which severely impacts device and circuit performance in advanced technologies and requires statistical compact models Promotes further research of the evolution and development of compact models for VLSI circuit design and analysis Supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices Includes exercise problems at the end of each chapter and extensive references at the end of the book Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond is intended for senior undergraduate and graduate courses in electrical and electronics engineering as well as for researchers and practitioners working in the area of electron devices. However, even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts from this book.
Author: Amara Amara Publisher: Springer Science & Business Media ISBN: 1402093411 Category : Technology & Engineering Languages : en Pages : 215
Book Description
Until the 1990s, the reduction of the minimum feature sizes used to fabricate in- grated circuits, called “scaling”, has highlighted serious advantages as integration density, speed, power consumption, functionality and cost. Direct consequence was the decrease of cost-per-function, so the electronic productivity has largely progressed in this period. Another usually cited trend is the evolution of the in- gration density as expressed by the well-know Moore’s Law in 1975: the number of devices per chip doubles every 2 years. This evolution has allowed improving signi?cantly the circuit complexity, offering a great computing power in the case of microprocessor, for example. However, since few years, signi?cant issues appeared such as the increase of the circuit heating, device complexity, variability and dif?culties to improve the integration density. These new trends generate an important growth in development and production costs. Though is it, since 40 years, the evolution of the microelectronics always f- lowed the Moore’s law and each dif?culty has found a solution.
Author: Yogesh Singh Chauhan Publisher: Academic Press ISBN: 0124200850 Category : Technology & Engineering Languages : en Pages : 305
Book Description
This book is the first to explain FinFET modeling for IC simulation and the industry standard – BSIM-CMG - describing the rush in demand for advancing the technology from planar to 3D architecture, as now enabled by the approved industry standard. The book gives a strong foundation on the physics and operation of FinFET, details aspects of the BSIM-CMG model such as surface potential, charge and current calculations, and includes a dedicated chapter on parameter extraction procedures, providing a step-by-step approach for the efficient extraction of model parameters. With this book you will learn: Why you should use FinFET The physics and operation of FinFET Details of the FinFET standard model (BSIM-CMG) Parameter extraction in BSIM-CMG FinFET circuit design and simulation Authored by the lead inventor and developer of FinFET, and developers of the BSIM-CM standard model, providing an experts’ insight into the specifications of the standard The first book on the industry-standard FinFET model - BSIM-CMG
Author: K. Sivasankaran Publisher: Springer Nature ISBN: 981990157X Category : Computers Languages : en Pages : 98
Book Description
This book discusses the evolution of multigate transistors, the design challenges of transistors for high-frequency applications, and the design and modeling of multigate transistors for high-frequency applications. The contents particularly focus on the cut-off frequency and maximum oscillation frequency of different multigate structures. RF stability modeling for multigate transistors is presented, which can help to understand the relation between the small-signal parameter and the physical parameter of the device for optimization. This is a useful reference to those in academia and industry.
Author: Chenming Hu Publisher: Woodhead Publishing ISBN: 0081024029 Category : Technology & Engineering Languages : en Pages : 260
Book Description
Industry Standard FDSOI Compact Model BSIM-IMG for IC Design helps readers develop an understanding of a FDSOI device and its simulation model. It covers the physics and operation of the FDSOI device, explaining not only how FDSOI enables further scaling, but also how it offers unique possibilities in circuits. Following chapters cover the industry standard compact model BSIM-IMG for FDSOI devices. The book addresses core surface-potential calculations and the plethora of real devices and potential effects. Written by the original developers of the industrial standard model, this book is an excellent reference for the new BSIM-IMG compact model for emerging FDSOI technology. The authors include chapters on step-by-step parameters extraction procedure for BSIM-IMG model and rigorous industry grade tests that the BSIM-IMG model has undergone. There is also a chapter on analog and RF circuit design in FDSOI technology using the BSIM-IMG model. - Provides a detailed discussion of the BSIM-IMG model and the industry standard simulation model for FDSOI, all presented by the developers of the model - Explains the complex operation of the FDSOI device and its use of two independent control inputs - Addresses the parameter extraction challenges for those using this model
Author: Gajanan Dessai
Author: Gajanan Dessai
Author: J.-P. Colinge
Author: Matthew Thomas Donizetti
Author: Yogesh Singh Chauhan
Author: Gennady Gildenblat
Author: Samar K. Saha
Author: Amara Amara
Author: Yogesh Singh Chauhan
Author: K. Sivasankaran
Author: Chenming Hu