Built-in Test of CMOS Structured Logic with Realistic Fault Models PDF Download

Author: Mehdi Katoozi
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 204

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Author: F. Joel Ferguson
Publisher:
ISBN:
Category : Computer-aided design
Languages : en
Pages : 28

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Book Description
Abstract: "Two approaches have been used to balance the cost of generating effective tests for ICs and the need to increase the IC's quality level. The first approach favors using high-level fault models to reduce test generation costs at the expense of test quality, and the second approach favors the use of low-level, technology-specific fault models to increase defect coverage but lead to unacceptably high test generation costs. In this report we (1) present the results of simulations of complete single stuck-at test sets against a low-level model of bridge defects showing that an unacceptably high percentage of such defects are not detected by the complete stuck-at test sets; (2) show how low-level bridge fault models can be incorporated into high-level test generation; and (3) describe our system for generating effective tests for bridge faults and report on its performance."

Author: Ming-Bo Lin
Publisher: CRC Press
ISBN: 143986859X
Category : Technology & Engineering
Languages : en
Pages : 917

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Book Description
With the advance of semiconductors and ubiquitous computing, the use of system-on-a-chip (SoC) has become an essential technique to reduce product cost. With this progress and continuous reduction of feature sizes, and the development of very large-scale integration (VLSI) circuits, addressing the harder problems requires fundamental understanding of circuit and layout design issues. Furthermore, engineers can often develop their physical intuition to estimate the behavior of circuits rapidly without relying predominantly on computer-aided design (CAD) tools. Introduction to VLSI Systems: A Logic, Circuit, and System Perspective addresses the need for teaching such a topic in terms of a logic, circuit, and system design perspective. To achieve the above-mentioned goals, this classroom-tested book focuses on: Implementing a digital system as a full-custom integrated circuit Switch logic design and useful paradigms that may apply to various static and dynamic logic families The fabrication and layout designs of complementary metal-oxide-semiconductor (CMOS) VLSI Important issues of modern CMOS processes, including deep submicron devices, circuit optimization, interconnect modeling and optimization, signal integrity, power integrity, clocking and timing, power dissipation, and electrostatic discharge (ESD) Introduction to VLSI Systems builds an understanding of integrated circuits from the bottom up, paying much attention to logic circuit, layout, and system designs. Armed with these tools, readers can not only comprehensively understand the features and limitations of modern VLSI technologies, but also have enough background to adapt to this ever-changing field.

Author: George W. Zobrist
Publisher: Praeger
ISBN:
Category : Computers
Languages : en
Pages : 216

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Book Description
VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed.

Author: F.P.M. Beenker
Publisher: Springer Science & Business Media
ISBN: 1461523656
Category : Technology & Engineering
Languages : en
Pages : 216

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Book Description
Preface Testing Integrated Circuits for manufacturing defects includes four basic disciplines. First of all an understanding of the origin and behaviour of defects. Secondly, knowledge of IC design and IC design styles. Thirdly, knowledge of how to create a test program for an IC which is targeted on detecting these defects, and finally, understanding of the hardware, Automatic Test Equipment, to run the test on. All four items have to be treated, managed, and to a great extent integrated before the term 'IC quality' gets a certain meaning and a test a certain measurable value. The contents of this book reflects our activities on testability concepts for complex digital ICs as performed at Philips Research Laboratories in Eindhoven, The Netherlands. Based on the statements above, we have worked along a long term plan, which was based on four pillars. 1. The definition of a test methodology suitable for 'future' IC design styles, 2. capable of handling improved defect models, 3. supported by software tools, and 4. providing an easy link to Automatic Test Equipment. The reasoning we have followed was continuously focused on IC qUality. Quality expressed in terms of the ability of delivering a customer a device with no residual manufacturing defects. Bad devices should not escape a test. The basis of IC quality is a thorough understanding of defects and defect models.

Author:
Publisher:
ISBN:
Category : Dissertations, Academic
Languages : en
Pages : 788

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Author: Alvin Lun-Knep Jee
Publisher:
ISBN:
Category : Fault-tolerant computing
Languages : en
Pages : 98

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Book Description
Abstract: "Traditional fault models for testing CMOS VLSI circuits do not take into account the actual mechanisms that precipitate faults. As a result, the failure modes of a circuit as predicted by these fault models may not reflect the realistic failure modes of the circuit. This thesis reports on the Carafe software which determines the realistic bridge faults of a CMOS circuit based on its layout. Each fault found by Carafe is assigned a relative probability based on the geometry of the fault site and defect distributions of the fabrication process. Carafe improves upon previous software in that it is easier to use, more robust, and more time and memory efficient so that larger circuits can be analyzed."

Author: A. Christou
Publisher: Springer Science & Business Media
ISBN: 9400924828
Category : Technology & Engineering
Languages : en
Pages : 571

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Book Description
This publication is a compilation of papers presented at the Semiconductor Device Reliabi lity Workshop sponsored by the NATO International Scientific Exchange Program. The Workshop was held in Crete, Greece from June 4 to June 9, 1989. The objective of the Workshop was to review and to further explore advances in the field of semiconductor reliability through invited paper presentations and discussions. The technical emphasis was on quality assurance and reliability of optoelectronic and high speed semiconductor devices. The primary support for the meeting was provided by the Scientific Affairs Division of NATO. We are indebted to NATO for their support and to Dr. Craig Sinclair, who admin isters this program. The chapters of this book follow the format and order of the sessions of the meeting. Thirty-six papers were presented and discussed during the five-day Workshop. In addi tion, two panel sessions were held, with audience participation, where the particularly controversial topics of bum-in and reliability modeling and prediction methods were dis cussed. A brief review of these sessions is presented in this book.

Author: Robert J. Nesbitt
Publisher:
ISBN:
Category :
Languages : en
Pages : 260

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Book Description

Author: Manoj Sachdev
Publisher: Springer Science & Business Media
ISBN: 1475749260
Category : Technology & Engineering
Languages : en
Pages : 317

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Book Description
Defect oriented testing is expected to play a significant role in coming generations of technology. Smaller feature sizes and larger die sizes will make ICs more sensitive to defects that can not be modeled by traditional fault modeling approaches. Furthermore, with increased level of integration, an IC may contain diverse building blocks. Such blocks include, digital logic, PLAs, volatile and non-volatile memories, and analog interfaces. For such diverse building blocks, traditional fault modeling and test approaches will become increasingly inadequate. Defect oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits (ICs) have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of highest possible quality. Testing, in general and, defect oriented testing, in particular, help in realizing these objectives. Defect Oriented Testing for CMOS Analog and Digital Circuits is the first book to provide a complete overview of the subject. It is essential reading for all design and test professionals as well as researchers and students working in the field. `A strength of this book is its breadth. Types of designs considered include analog and digital circuits, programmable logic arrays, and memories. Having a fault model does not automatically provide a test. Sometimes, design for testability hardware is necessary. Many design for testability ideas, supported by experimental evidence, are included.' ... from the Foreword by Vishwani D. Agrawal