Author: Michele RiccioPublisher: Trans Tech Publications Ltd
ISBN: 3036416471
Category : Science
Languages : en
Pages : 126
Book Description
Special topic volume with invited peer-reviewed papers only
Solid-State Power Devices: Operational Reliability and Parameters' Stability
Author: Michele RiccioPublisher: Trans Tech Publications Ltd
ISBN: 3036416471
Category : Science
Languages : en
Pages : 126
Book Description
Special topic volume with invited peer-reviewed papers only
Fundamentals of Bias Temperature Instability in MOS Transistors
Author: Souvik MahapatraPublisher: Springer
ISBN: 8132225082
Category : Technology & Engineering
Languages : en
Pages : 282
Book Description
This book aims to cover different aspects of Bias Temperature Instability (BTI). BTI remains as an important reliability concern for CMOS transistors and circuits. Development of BTI resilient technology relies on utilizing artefact-free stress and measurement methods and suitable physics-based models for accurate determination of degradation at end-of-life and understanding the gate insulator process impact on BTI. This book discusses different ultra-fast characterization techniques for recovery artefact free BTI measurements. It also covers different direct measurements techniques to access pre-existing and newly generated gate insulator traps responsible for BTI. The book provides a consistent physical framework for NBTI and PBTI respectively for p- and n- channel MOSFETs, consisting of trap generation and trapping. A physics-based compact model is presented to estimate measured BTI degradation in planar Si MOSFETs having differently processed SiON and HKMG gate insulators, in planar SiGe MOSFETs and also in Si FinFETs. The contents also include a detailed investigation of the gate insulator process dependence of BTI in differently processed SiON and HKMG MOSFETs. The book then goes on to discuss Reaction-Diffusion (RD) model to estimate generation of new traps for DC and AC NBTI stress and Transient Trap Occupancy Model (TTOM) to estimate charge occupancy of generated traps and their contribution to BTI degradation. Finally, a comprehensive NBTI modeling framework including TTOM enabled RD model and hole trapping to predict time evolution of BTI degradation and recovery during and after DC stress for different stress and recovery biases and temperature, during consecutive arbitrary stress and recovery cycles and during AC stress at different frequency and duty cycle. The contents of this book should prove useful to academia and professionals alike.
Bias Temperature Instability for Devices and Circuits
Author: Tibor GrasserPublisher: Springer Science & Business Media
ISBN: 1461479096
Category : Technology & Engineering
Languages : en
Pages : 805
Book Description
This book provides a single-source reference to one of the more challenging reliability issues plaguing modern semiconductor technologies, negative bias temperature instability. Readers will benefit from state-of-the art coverage of research in topics such as time dependent defect spectroscopy, anomalous defect behavior, stochastic modeling with additional metastable states, multiphonon theory, compact modeling with RC ladders and implications on device reliability and lifetime.
Microelectronic Test Structures for CMOS Technology
Author: Manjul BhushanPublisher: Springer Science & Business Media
ISBN: 1441993770
Category : Technology & Engineering
Languages : en
Pages : 401
Book Description
Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance and characteristics of MOSFETs and other circuit elements. Detailed examples are presented throughout, many of which are equally applicable to other microelectronic technologies as well. The authors’ overarching goal is to provide students and technology practitioners alike a practical guide to the disciplined design and use of test structures that give unambiguous information on the parametrics and performance of digital CMOS technology.
Reliability of high-k / metal gate field-effect transistors considering circuit operational constraints
Author: Steve KupkePublisher: BoD – Books on Demand
ISBN: 3741208698
Category : Technology & Engineering
Languages : en
Pages : 125
Book Description
After many decades, the scaling of silicon dioxide based field-effect transistors has reached insurmountable physical limits due unintentional high gate leakage currents for gate oxide thicknesses below 2 nm. The introduction of high-k metal gate stacks guaranteed the trend towards smaller transistor dimensions. The implementation of HfO2, as high-k dielectric, also lead to a substantial number of manufacturing and reliability challenges. The deterioration of the gate oxide properties under thermal and electric stress jeopardizes the circuit operation and hence needs to be comprehensively understood. As a starting point, 6T static random access memory cells were used to identify the different single device operating conditions. The strongest deterioration of the gate stack was found for nMOS devices under positive bias temperature instability (PBTI) stress, resulting in a severe threshold voltage shift and increased gate leakage current. A detailed investigation of physical origin and temperature and voltage dependency was done. The reliability issues were caused by the electron trapping into already existing HfO2 oxygen vacancies. The oxygen vacancies reside in different charge states depending on applied stress voltages. This in return also resulted in a strong threshold voltage and gate current relaxation after stress was cut off. The reliability assessment using constant voltage stress does not reflect realistic circuit operation which can result in a changed degradation behaviour. Therefore, the constant voltage stress measurement were extended by considering CMOS operational constraints, where it was found that the supply voltage frequently switches between the gate and drain terminal. The additional drain (off-state) bias lead to an increased Vt relaxation in comparison to zero bias voltage. The off-state influence strongly depended on the gate length and became significant for short channel devices. The influence of the off-state bias on the dielectric breakdown was studied and compared to the standard assessment methods. Different wear-out mechanisms for drain-only and alternating gate and drain stress were verified. Under drain-only stress, the dielectric breakdown was caused by hot carrier degradation. The lifetime was correlated with the device length and amount of subthreshold leakage. The gate oxide breakdown under alternating gate and o-state stress was caused by the continuous trapping and detrapping behaviour of high-k metal gate devices.
Scientific and Technical Aerospace Reports
Author: JJAP
Author: Physics and Technology of High-k Materials 9
Author: S. KarPublisher: The Electrochemical Society
ISBN: 1607682575
Category :
Languages : en
Pages : 504
Book Description
NASA Scientific and Technical Reports and Publications for 1969 - A Selected Listing
Author: United States. National Aeronautics and Space Administration. Scientific and Technical Information DivisionPublisher:
ISBN:
Category : Science
Languages : en
Pages : 956
Book Description
NASA Scientific and Technical Reports
Author: United States. National Aeronautics and Space Administration Scientific and Technical Information DivisionPublisher:
ISBN:
Category : Aeronautics
Languages : en
Pages : 966
Book Description