Author: Veit B. KleebergerPublisher:
ISBN:
Category :
Languages : en
Pages : 40
Book Description
Aging Aware Timing Analysis of Digital Integrated Circuits for Varying Use Profiles
Author: Veit B. KleebergerTechniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits
Author: Suryanarayana PendelaPublisher:
ISBN:
Category :
Languages : en
Pages : 95
Book Description
Much of the Semiconductor Industry's success can be attributed to Moore's law which states that the number of transistors on an integrated circuit would double approximately every two years. Semiconductor industry has ever since progressed from designs with a few hundred transistors to today's complex designs incorporating millions of transistors. The current era of nanometer technologies threatens to impact the sustainability of Moore's law with random variations in the manufacturing process impacting yield in a big way. Considerable research efforts have since been devoted to account for these variations leading to a new paradigm called Design for Manufacturing (DFM). Traditional Static Timing Analysis (STA) has given way to Statistical Static Timing Analysis (SSTA) techniques wherein the parameters considered are treated as random variables with assigned probability distribution functions. However, SSTA is still not seen as a mature flow for commercial adoption, owing to the inherent complex nature of the SSTA algorithms. In this thesis, we propose an alternate framework to STA under the presence of process variations using Interval Valued Static Timing Analysis (IVSTA). Process variations are accounted for by using a macro-modeling framework providing an efficient and fast timing analysis technique. Results on standard benchmarks show that IVSTA can predict the timing slack by a margin of 5-10% error and huge improvement of runtime compared to traditional corner based analysis. The framework involves a one-time characterization of the standard cell library and can be incorporated without much modification to the design flow. An iterative optimization framework using IVSTA engine is also presented which optimizes a routed netlist for variations at a minimum penalty of area and power.
Ageing of Integrated Circuits
Author: Basel HalakPublisher: Springer Nature
ISBN: 3030237818
Category : Technology & Engineering
Languages : en
Pages : 228
Book Description
This book provides comprehensive coverage of the latest research into integrated circuits’ ageing, explaining the causes of this phenomenon, describing its effects on electronic systems, and providing mitigation techniques to build ageing-resilient circuits.
Aging Analysis of Digital Integrated Circuits
Author: Dominik LorenzVariation-aware and Aging-aware Design Tools and Techniques for Nanometer-scale Integrated Circuits
Author: Saket GuptaLogic-level timing analysis for digital integrated circuits
Author: Chanhee OhPublisher:
ISBN:
Category : Digital integrated circuits
Languages : en
Pages : 184
Book Description
Author: Jiayong Le
Author: 
Author: Khaled R. Heloue
Author: Nico Hellwege