Author: Dominik LorenzPublisher:
ISBN:
Category :
Languages : en
Pages : 150
Book Description
Aging Analysis of Digital Integrated Circuits
Author: Dominik LorenzAging Aware Timing Analysis of Digital Integrated Circuits for Varying Use Profiles
Author: Veit B. KleebergerAgeing of Integrated Circuits
Author: Basel HalakPublisher: Springer Nature
ISBN: 3030237818
Category : Technology & Engineering
Languages : en
Pages : 228
Book Description
This book provides comprehensive coverage of the latest research into integrated circuits’ ageing, explaining the causes of this phenomenon, describing its effects on electronic systems, and providing mitigation techniques to build ageing-resilient circuits.
Experimental Analysis on Aging of Integrated Circuits
Author: Niranjan Reddy KayamPublisher:
ISBN:
Category :
Languages : en
Pages : 188
Book Description
Experimental Analysis on Aging of Integrated Circuits
Author: Niranjan Reddy KayamLifetime Reliability-aware Design of Integrated Circuits
Author: Mohsen RajiPublisher: Springer Nature
ISBN: 3031153456
Category : Technology & Engineering
Languages : en
Pages : 113
Book Description
This book covers the state-of-the-art research in design of modern electronic systems used in safety-critical applications such as medical devices, aircraft flight control, and automotive systems. The authors discuss lifetime reliability of digital systems, as well as an overview of the latest research in the field of reliability-aware design of integrated circuits. They address modeling approaches and techniques for evaluation and improvement of lifetime reliability for nano-scale CMOS digital circuits, as well as design algorithms that are the cornerstone of Computer Aided Design (CAD) of reliable VLSI circuits. In addition to developing lifetime reliability analysis and techniques for clocked storage elements (such as flip-flops), the authors also describe analysis and improvement strategies targeting commercial digital circuits.
Analog IC Reliability in Nanometer CMOS
Author: Elie MaricauPublisher: Springer Science & Business Media
ISBN: 1461461634
Category : Technology & Engineering
Languages : en
Pages : 208
Book Description
This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed. The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.
CMOS Digital Integrated Circuits
Author: Sung-Mo KangPublisher:
ISBN: 9780071243421
Category : Digital integrated circuits
Languages : en
Pages : 655
Book Description
The fourth edition of CMOS Digital Integrated Circuits: Analysis and Design continues the well-established tradition of the earlier editions by offering the most comprehensive coverage of digital CMOS circuit design, as well as addressing state-of-the-art technology issues highlighted by the widespread use of nanometer-scale CMOS technologies. In this latest edition, virtually all chapters have been re-written, the transistor model equations and device parameters have been revised to reflect the sigificant changes that must be taken into account for new technology generations, and the material has been reinforced with up-to-date examples. The broad-ranging coverage of this textbook starts with the fundamentals of CMOS process technology, and continues with MOS transistor models, basic CMOS gates, interconnect effects, dynamic circuits, memory circuits, arithmetic building blocks, clock and I/O circuits, low power design techniques, design for manufacturability and design for testability.
Multilevel Aging Phenomena Analysis in Complex Ultimate CMOS Designs
Author: Dolly Natalia Ruiz AmadorPublisher:
ISBN:
Category :
Languages : en
Pages : 0
Book Description
Integrated circuits evolution is driven by the trend of increasing operating frequencies and downscaling of the device size, while embedding more and more complex functionalities in a single chip. However, the continuation of the device-scaling race generates a number of technology challenges. For instance, the downscaling of transistor channel lengths induce short-channel effects (drain-induced barrier lowering and punch-through phenomena); high electric field in the devices tend to increase Hot electron effect (or Hot Carrier) and Oxide Dielectric Breakdown; higher temperatures in IC products generates an increase of the Negative Bias Temperature Instability (NBTI) effect on pMOS devices. Today, it is considered that the above reliability mechanisms are ones of the main causes of circuit degradation performance in the field. This dissertation will address the Hot Carrier (HC) and NBTI impacts on CMOS product electrical performances. A CAD bottom-up approach will be proposed and analyzed, based on the Design-in Reliability (DiR) methodology. With this purpose, a detailed analysis of the NBTI and the HC behaviours and their impact at different abstraction level is provided throughout this thesis. First, a physical framework presenting the NBTI and the HC mechanisms is given, focusing on electrical parameters weakening of nMOS and pMOS transistors. Moreover, the main analytical HC and NBTI degradation models are treated in details. In the second part, the delay degradation of digital standard cells due to NBTI, HCI is shown; an in-depth electrical CAD analysis illustrates the combined effects of design parameters and HCI/NBTI on the timing performance of standard cells. Additionally, a gate level approach is developed, in which HC and NBTI mechanisms are individually addressed. The consequences of the degradation at system level are presented in the third part of the thesis. With this objective, data extracted from silicon measures are compared against CAD estimations on two complexes IPs fabricated on STCMOS 45nm technologies. It is expected that the findings of this thesis highly contribute to the understanding of the NBTI and HC reliability wearout mechanisms at the system level.STAR.
An Examination of CMOS Aging in Integrated Circuits and Novel Aging Detection Techniques for SRAM Cells
Author: Gates Richmond WinklerPublisher:
ISBN: 9781267298157
Category :
Languages : en
Pages : 37
Book Description
This thesis work examines the problem of CMOS aging in VLSI integrated circuits. In nanoscale technologies, Negative and Positive Bias Temperature Instability causes an increase over time in the absolute value of the threshold voltage of PMOS and NMOS transistors which results in degraded circuit performance. Current methods to detect and compensate for aging in both digital and combinational logic and memory arrays are presented in this work. My own research contribution in the field of SRAM aging detection is then described. Modifications to standard 6T SRAM cells create a built in sensor which can detect effects of Bias Temperature Instability on the NMOS and PMOS transistors of an SRAM cell. The proposed design allows for a check process, which can observe an increase in transistor threshold voltage as a result of aging effects directly in a cell which is actually used as a memory unit. The proposed modifications allow for detections of aging while having a minimized impact on area and performance of a standard 6T SRAM cell.