Author: Reinaldo A. VegaPublisher:
ISBN:
Category :
Languages : en
Pages : 0
Book Description
Advanced Source/drain and Contact Design for Nanoscale CMOS
Author: Reinaldo A. VegaAdvanced Source/drain and Contact Design for Nanoscale CMOS
Author: Reinaldo A. VegaAdvanced Source/drain Technologies for Nanoscale CMOS
Author: Pankaj KalraNanoscale CMOS
Author: Francis BalestraPublisher: John Wiley & Sons
ISBN: 1118622472
Category : Technology & Engineering
Languages : en
Pages : 518
Book Description
This book provides a comprehensive review of the state-of-the-art in the development of new and innovative materials, and of advanced modeling and characterization methods for nanoscale CMOS devices. Leading global industry bodies including the International Technology Roadmap for Semiconductors (ITRS) have created a forecast of performance improvements that will be delivered in the foreseeable future – in the form of a roadmap that will lead to a substantial enlargement in the number of materials, technologies and device architectures used in CMOS devices. This book addresses the field of materials development, which has been the subject of a major research drive aimed at finding new ways to enhance the performance of semiconductor technologies. It covers three areas that will each have a dramatic impact on the development of future CMOS devices: global and local strained and alternative materials for high speed channels on bulk substrate and insulator; very low access resistance; and various high dielectric constant gate stacks for power scaling. The book also provides information on the most appropriate modeling and simulation methods for electrical properties of advanced MOSFETs, including ballistic transport, gate leakage, atomistic simulation, and compact models for single and multi-gate devices, nanowire and carbon-based FETs. Finally, the book presents an in-depth investigation of the main nanocharacterization techniques that can be used for an accurate determination of transport parameters, interface defects, channel strain as well as RF properties, including capacitance-conductance, improved split C-V, magnetoresistance, charge pumping, low frequency noise, and Raman spectroscopy.
Advanced Nanoscale MOSFET Architectures
Author: Kalyan BiswasPublisher: John Wiley & Sons
ISBN: 1394188951
Category : Technology & Engineering
Languages : en
Pages : 340
Book Description
Comprehensive reference on the fundamental principles and basic physics dictating metal–oxide–semiconductor field-effect transistor (MOSFET) operation Advanced Nanoscale MOSFET Architectures provides an in-depth review of modern metal–oxide–semiconductor field-effect transistor (MOSFET) device technologies and advancements, with information on their operation, various architectures, fabrication, materials, modeling and simulation methods, circuit applications, and other aspects related to nanoscale MOSFET technology. The text begins with an introduction to the foundational technology before moving on to describe challenges associated with the scaling of nanoscale devices. Other topics covered include device physics and operation, strain engineering for highly scaled MOSFETs, tunnel FET, graphene based field effect transistors, and more. The text also compares silicon bulk and devices, nanosheet transistors and introduces low-power circuit design using advanced MOSFETs. Additional topics covered include: High-k gate dielectrics and metal gate electrodes for multi-gate MOSFETs, covering gate stack processing and metal gate modification Strain engineering in 3D complementary metal-oxide semiconductors (CMOS) and its scaling impact, and strain engineering in silicon–germanium (SiGe) FinFET and its challenges and future perspectives TCAD simulation of multi-gate MOSFET, covering model calibration and device performance for analog and RF applications Description of the design of an analog amplifier circuit using digital CMOS technology of SCL for ultra-low power VLSI applications Advanced Nanoscale MOSFET Architectures helps readers understand device physics and design of new structures and material compositions, making it an important resource for the researchers and professionals who are carrying out research in the field, along with students in related programs of study.
Low Resistivity Contact Methodologies for Silicon, Silicon Germanium and Silicon Carbon Source/drain Junctions of Nanoscale CMOS Integrated Circuits
Author: Emre AlptekinPublisher:
ISBN:
Category :
Languages : en
Pages : 92
Book Description
Keywords: silicon carbon, silicide, barrier height, contact resistance, MOSFET, source drain junction.
Advanced Gate Stack, Source/drain and Channel Engineering for Si-based CMOS
Author: Publisher:
ISBN:
Category : Technology & Engineering
Languages : en
Pages : 658
Book Description
Nano-CMOS Circuit and Physical Design
Author: Ban WongPublisher: John Wiley & Sons
ISBN: 0471678864
Category : Technology & Engineering
Languages : en
Pages : 413
Book Description
Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength optical lithography; impact of process scaling on circuit and physical implementation and low power with leaky transistors; and DFM, yield, and the impact of physical implementation.
Modeling and Optimal Design of Nanoscale Double-Gate CMOS Devices and Technology
Author: Shishir AgrawalPublisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
We present a physical model for fringe capacitance (C[subscript]f) in DG MOSFETs with non-abrupt S/D junctions. We model Cf in terms of the device structure and short-channel effects (SCEs). The model is implemented in our physical/process based compact model, UFDG, and will enable quasi-predictive device/circuit simulations. In undoped UTB FinFETs, the lateral S/D doping profile, N[subscriptSD](y), defines the tradeoff between SCEs and parasitic resistance, R[subscript]S/D, via gate-source/drain underlap. We demonstrate a reverse-engineering methodology to extract N[subscriptSD](y) from FinFET C[subscriptG]-V[subscript]GS and I[subscriptDS]-V[subscript]GS data. The extracted N[subscriptSD](y) is then used to redesign the S/D process to effect a better tradeoff between SCEs and R[subscript]S/D. Finally, we discuss the degradation of mobility in short-channel FinFETs possibly due to S/D defects/dopants. We explore possible causes of the phenomenon and make device processing suggestions to help mitigate the effect.
Nanometer CMOS
Author: Juin J. LiouPublisher: CRC Press
ISBN: 1466511702
Category : Science
Languages : en
Pages : 268
Book Description
This book presents the material necessary for understanding the physics, operation, design, and performance of modern MOSFETs with nanometer dimensions. It offers a brief introduction to the field and a thorough overview of MOSFET physics, detailing the relevant basics. The authors apply presented models to calculate and demonstrate transistor characteristics, and they include required input data (e.g., dimensions, doping) enabling readers to repeat the calculations and compare their results. The book introduces conventional and novel advanced MOSFET concepts, such as multiple-gate structures or alternative channel materials. Other topics covered include high-k dielectrics and mobility enhancement techniques, MOSFETs for RF (radio frequency) applications, MOSFET fabrication technology.