Author: Aniruddha S. Vaidya
Publisher:
ISBN:
Category : Computer networks
Languages : en
Pages : 20
Book Description
Abstract: "With parallel machines increasingly taking on critical and complex applications, it is important to make them dependable to ensure their commercial success. Fault-tolerance in the network to accommodate link and node failures is an important step towards this goal. This can be achieved by employing cost-effective fault-tolerant algorithms. However, despite substantial efforts on the theoretical front in developing fault-tolerant routing techniques and architectures, these ideas have not manifested themselves in many commercial platforms. The ramifications of providing fault-tolerant routing in terms of cost and performance is still not clear to the computer architect. Such an insight can only be gained through detailed analysis of a design with realistic workloads. Since no current evaluation platform supports this, previous research on fault-tolerant routing has used synthetic workloads for analyzing performance. This paper presents a comprehensive evaluation testbed for interconnection networks and routing algorithms using real applications. The testbed is flexible enough to implement any network topology and fault-tolerant routing algorithm, and allows the system architect to study the cost versus performance tradeoffs for a range of network parameters. We illustrate its use with one fault-tolerant algorithm and analyze the performance of four shared memory applications with different fault conditions. We also show how the testbed can be used to drive future research in fault-tolerant routing algorithms and architectures, by proposing and evaluating novel architectural enhancements to the network router, called path selection heuristics (PSH). We propose three such schemes and the Least Recently Used (LRU) PSH is shown to give the best performance in the presence of faults."
A Testbed for Evaluation of Fault-tolerant Routing in Multiprocessor Interconnection Networks
Author: Aniruddha S. Vaidya
Publisher:
ISBN:
Category : Computer networks
Languages : en
Pages : 20
Book Description
Abstract: "With parallel machines increasingly taking on critical and complex applications, it is important to make them dependable to ensure their commercial success. Fault-tolerance in the network to accommodate link and node failures is an important step towards this goal. This can be achieved by employing cost-effective fault-tolerant algorithms. However, despite substantial efforts on the theoretical front in developing fault-tolerant routing techniques and architectures, these ideas have not manifested themselves in many commercial platforms. The ramifications of providing fault-tolerant routing in terms of cost and performance is still not clear to the computer architect. Such an insight can only be gained through detailed analysis of a design with realistic workloads. Since no current evaluation platform supports this, previous research on fault-tolerant routing has used synthetic workloads for analyzing performance. This paper presents a comprehensive evaluation testbed for interconnection networks and routing algorithms using real applications. The testbed is flexible enough to implement any network topology and fault-tolerant routing algorithm, and allows the system architect to study the cost versus performance tradeoffs for a range of network parameters. We illustrate its use with one fault-tolerant algorithm and analyze the performance of four shared memory applications with different fault conditions. We also show how the testbed can be used to drive future research in fault-tolerant routing algorithms and architectures, by proposing and evaluating novel architectural enhancements to the network router, called path selection heuristics (PSH). We propose three such schemes and the Least Recently Used (LRU) PSH is shown to give the best performance in the presence of faults."
Publisher:
ISBN:
Category : Computer networks
Languages : en
Pages : 20
Book Description
Abstract: "With parallel machines increasingly taking on critical and complex applications, it is important to make them dependable to ensure their commercial success. Fault-tolerance in the network to accommodate link and node failures is an important step towards this goal. This can be achieved by employing cost-effective fault-tolerant algorithms. However, despite substantial efforts on the theoretical front in developing fault-tolerant routing techniques and architectures, these ideas have not manifested themselves in many commercial platforms. The ramifications of providing fault-tolerant routing in terms of cost and performance is still not clear to the computer architect. Such an insight can only be gained through detailed analysis of a design with realistic workloads. Since no current evaluation platform supports this, previous research on fault-tolerant routing has used synthetic workloads for analyzing performance. This paper presents a comprehensive evaluation testbed for interconnection networks and routing algorithms using real applications. The testbed is flexible enough to implement any network topology and fault-tolerant routing algorithm, and allows the system architect to study the cost versus performance tradeoffs for a range of network parameters. We illustrate its use with one fault-tolerant algorithm and analyze the performance of four shared memory applications with different fault conditions. We also show how the testbed can be used to drive future research in fault-tolerant routing algorithms and architectures, by proposing and evaluating novel architectural enhancements to the network router, called path selection heuristics (PSH). We propose three such schemes and the Least Recently Used (LRU) PSH is shown to give the best performance in the presence of faults."
Fault-tolerant Multiprocessor Interconnection Networks and Their Fault-diagnoses
Author: Nian-Feng Tzeng
Publisher:
ISBN:
Category : Electronic data processing
Languages : en
Pages : 260
Book Description
Publisher:
ISBN:
Category : Electronic data processing
Languages : en
Pages : 260
Book Description
Proceedings
Author:
Publisher:
ISBN:
Category : Computer architecture
Languages : en
Pages : 454
Book Description
Publisher:
ISBN:
Category : Computer architecture
Languages : en
Pages : 454
Book Description
Fault-tolerant Routing in Multistage Interconnection Networks
Author: International Business Machines Corporation. Research Division
Publisher:
ISBN:
Category :
Languages : en
Pages : 24
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 24
Book Description
Understanding and Coping with Failures in Large-scale Storage Systems
Efficient Fault-tolerant Routing and Embeddings in Interconnection Networks
Applied Science & Technology Index
Low Cost, Adaptive, Fault Tolerant Routing in Low Dimension Direct Interconnection Networks
Multipath fault-tolerant routing policies to deal with dynamic link failures in high speed interconnection networks
Fault Tolerant Broadcasting Algorithms for Interconnection Networks
Author: Nai-Wei Lo
Publisher:
ISBN:
Category : Algorithms
Languages : en
Pages : 242
Book Description
Publisher:
ISBN:
Category : Algorithms
Languages : en
Pages : 242
Book Description