Author: Aparna SrinivasanPublisher:
ISBN:
Category :
Languages : en
Pages : 179
Book Description
A Systematic Approach to Modeling Yield for Integrated Circuits
Author: Aparna SrinivasanYield Simulation for Integrated Circuits
Author: D.M. WalkerPublisher: Springer Science & Business Media
ISBN: 9780898382440
Category : Computers
Languages : en
Pages : 230
Book Description
In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself.
Integrated Circuit Manufacturability
Author: José Pineda de GyvezPublisher: John Wiley & Sons
ISBN: 0780334477
Category : Technology & Engineering
Languages : en
Pages : 338
Book Description
"INTEGRATED CIRCUIT MANUFACTURABILITY provides comprehensive coverage of the process and design variables that determine the ease and feasibility of fabrication (or manufacturability) of contemporary VLSI systems and circuits. This book progresses from semiconductor processing to electrical design to system architecture. The material provides a theoretical background as well as case studies, examining the entire design for the manufacturing path from circuit to silicon. Each chapter includes tutorial and practical applications coverage. INTEGRATED CIRCUIT MANUFACTURABILITY illustrates the implications of manufacturability at every level of abstraction, including the effects of defects on the layout, their mapping to electrical faults, and the corresponding approaches to detect such faults. The reader will be introduced to key practical issues normally applied in industry and usually required by quality, product, and design engineering departments in today's design practices: * Yield management strategies * Effects of spot defects * Inductive fault analysis and testing * Fault-tolerant architectures and MCM testing strategies. This book will serve design and product engineers both from academia and industry. It can also be used as a reference or textbook for introductory graduate-level courses on manufacturing."
Predictive Modeling of Integrated Circuit Manufacturing Variation
Author: Swamy V. MudduPublisher:
ISBN:
Category :
Languages : en
Pages : 190
Book Description
Continuous scaling of feature sizes in CMOS integrated circuits (IC) pushes the design performance envelope as well as design complexity higher with each successive technology node. Advancements in materials and optics of the manufacturing process enable the scaling and manufacturability of devices in ICs. As device feature dimensions approach the physical limits of lithography and the manufacturing process, the smallest geometric and material variations manifest as design-level performance and power variability. One of the main pathological effects of IC scaling is the increase in design variability as a fraction of performance with each technology node. This design variability directly affects IC parametric (i.e., performance-limited) and catastrophic (i.e., defect-limited) yield, and consequently, IC cost. To address the increase in manufacturing variability in deep-submicron (DSM) technologies and to improve IC yield, a new design for manufacturability (DFM) paradigm has emerged in the recent past. The DFM paradigm encompasses a set of design methodologies that address manufacturing and process non-idealities at the design level to make ICs more robust to variations. DFM is also interpreted as a set of post-layout design fixing techniques that enhance and ease manufacturability. In general, the objective of DFM is to improve IC yield and cost by increasing manufacturing-awareness in the design phase, as well as design-awareness in the manufacturing phase. To achieve this dual objective of DFM, design must be driven by models of variation in the manufacturing process and the manufacturing process, must be made aware of the design intent. Variations in the IC manufacturing process are manifested as (1) deviation from the intended shapes of IC geometries, and (2) variations in impurity (i.e., dopant) concentrations. These variations are composed of systematic and random components. The systematic component of variation can be attributed to specific sources in the manufacturing process, while the random component is usually a result of confounding of several sources of variation and cannot be attributed to specific sources. A significant fraction of the total variation in shapes of IC geometries is systematic in sources such as focus, exposure dose, lens aberrations, etc. The objective of this thesis is to model the impact of the raw sources of variation at the mask making and wafer pattern transfer phases in manufacturing. The primary goal in the associated research is to develop models that can drive systematic variation-aware design. We propose techniques to model the impact of mask-level and wafer-level sources of variation on IC geometries. At the mask-level, proximity effects and resist heating caused by electron-beam writing are the two main sources of mask critical dimension (CD) errors. We propose a novel methodology to model resist heating caused by electron-beam writing on the mask resist. We use the resist heating model to drive temperature-aware mask writing schedules that minimize resist temperature, and consequently minimize mask CD error. Sub-wavelength optical lithography in sub-100nm technology nodes is enabled by resolution enhancement techniques (RETs) that allow patterning of layout features on silicon wafers. Optical proximity correction (OPC) is the most prominent RET used to compensate a design layout for optical and process effects prior to mask making and lithography. OPC modifies the shapes of layout features, and consequently increases mask complexity and cost. We develop a model of post-OPC mask cost of design features, to drive design-aware mask cost optimization. Despite advanced RETs and illumination techniques, several sources of variation in the pattern transfer process result in variations in chip-level performance and power. At 45nm and below, accurate design-level performance and power analyses must consider litho-simulated non-idealities in patterning. However, the simulation of exposure, resist and etch processing steps in lithography is computationally expensive to perform at chip-scale, and essentially infeasible during iterative design optimization. In this thesis, We develop a predictive model of post-OPC linewidth of devices in standard cells across the process window. The predictive model is fast, accurate and highly scalable, enabling its use in the design phase at full-chip scale without actually performing OPC and litho simulation. Last, we demonstrate the use of predictive linewidth models in fast and accurate leakage estimation and optimization. First, We discuss the use of through-focus systematic linewidth models to achieve accurate leakage estimation. We then discuss a novel detailed placement perturbation approach that leverages systematic pitch and focus interactions to improve leakage in light of systematic linewidth variation. These two methods demonstrate the use of predictive models of variation in driving variation-aware design analysis and optimization.
Yield and Variability Optimization of Integrated Circuits
Author: Jian Cheng ZhangPublisher: Springer Science & Business Media
ISBN: 1461522250
Category : Technology & Engineering
Languages : en
Pages : 244
Book Description
Traditionally, Computer Aided Design (CAD) tools have been used to create the nominal design of an integrated circuit (IC), such that the circuit nominal response meets the desired performance specifications. In reality, however, due to the disturbances ofthe IC manufacturing process, the actual performancesof the mass produced chips are different than those for the nominal design. Even if the manufacturing process were tightly controlled, so that there were little variations across the chips manufactured, the environmentalchanges (e. g. those oftemperature, supply voltages, etc. ) would alsomakethe circuit performances vary during the circuit life span. Process-related performance variations may lead to low manufacturing yield, and unacceptable product quality. For these reasons, statistical circuit design techniques are required to design the circuit parameters, taking the statistical process variations into account. This book deals with some theoretical and practical aspects of IC statistical design, and emphasizes how they differ from those for discrete circuits. It de scribes a spectrum of different statistical design problems, such as parametric yield optimization, generalized on-target design, variability minimization, per formance tunning, and worst-case design. The main emphasis of the presen tation is placed on the principles and practical solutions for performance vari ability minimization. It is hoped that the book may serve as an introductory reference material for various groups of IC designers, and the methodologies described will help them enhance the circuit quality and manufacturability. The book containsseven chapters.
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Author: José L. AyalaPublisher: Springer
ISBN: 3642361579
Category : Computers
Languages : en
Pages : 266
Book Description
This book constitutes the refereed proceedings of the 22nd International Conference on Integrated Circuit and System Design, PATMOS 2012, held in Newcastle, UK Spain, in September 2012. The 25 revised full papers presented were carefully reviewed and selected from numerous submissions. The paper feature emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGAs. The technical program focus on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization.
Computer-Aided Design of Analog Integrated Circuits and Systems
Author: Rob A. RutenbarPublisher: John Wiley & Sons
ISBN: 047122782X
Category : Technology & Engineering
Languages : en
Pages : 773
Book Description
The tools and techniques you need to break the analog design bottleneck! Ten years ago, analog seemed to be a dead-end technology. Today, System-on-Chip (SoC) designs are increasingly mixed-signal designs. With the advent of application-specific integrated circuits (ASIC) technologies that can integrate both analog and digital functions on a single chip, analog has become more crucial than ever to the design process. Today, designers are moving beyond hand-crafted, one-transistor-at-a-time methods. They are using new circuit and physical synthesis tools to design practical analog circuits; new modeling and analysis tools to allow rapid exploration of system level alternatives; and new simulation tools to provide accurate answers for analog circuit behaviors and interactions that were considered impossible to handle only a few years ago. To give circuit designers and CAD professionals a better understanding of the history and the current state of the art in the field, this volume collects in one place the essential set of analog CAD papers that form the foundation of today's new analog design automation tools. Areas covered are: * Analog synthesis * Symbolic analysis * Analog layout * Analog modeling and analysis * Specialized analog simulation * Circuit centering and yield optimization * Circuit testing Computer-Aided Design of Analog Integrated Circuits and Systems is the cutting-edge reference that will be an invaluable resource for every semiconductor circuit designer and CAD professional who hopes to break the analog design bottleneck.
Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Author: Bertrand HochetPublisher: Springer Science & Business Media
ISBN: 3540441433
Category : Computers
Languages : en
Pages : 510
Book Description
This book constitutes the refereed proceedings of the 12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002, held in Seville, Spain in September 2002. The 37 revised full papers and 12 poster papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on arithmetics, low-level modeling and characterization, asynchronous and adiabatic techniques, CAD tools and algorithms, timing, gate-level modeling and design, and communications modeling and activity reduction.
Integrated Circuit and System Design
Author: Jos MonteiroPublisher:
ISBN: 9783642118036
Category :
Languages : en
Pages : 384
Book Description
Defect and Fault Tolerance in VLSI Systems
Author: C.H. StapperPublisher: Springer Science & Business Media
ISBN: 1475799578
Category : Technology & Engineering
Languages : en
Pages : 313
Book Description
Higher circuit densities, increasingly more complex application ohjectives, and advanced packaging technologies have suhstantially increased the need to incorporate defect-tolerance and fault-tolerance in the design of VLSI and WSI systems. The goals of defect-tolerance and fault-tolerance are yield enhancement and improved reliahility. The emphasis on this area has resulted in a new field of interdisciplinary scientific research. I n fact, advanced methods of defect/fault control and tolerance are resulting in enhanced manufacturahility and productivity of integrated circuit chips, VI.SI systems, and wafer scale integrated circuits. In 1987, Dr. W. Moore organized an "International Workshop on Designing for Yield" at Oxford University. Edited papers of that workshop were published in reference [II. The participants in that workshop agreed that meetings of this type should he con tinued. preferahly on a yearly hasis. It was Dr. I. Koren who organized the "IEEE Inter national Workshop on Defect and Fault Tolerance in VLSI Systems" in Springfield Massachusetts the next year. Selected papers from that workshop were puhlished as the first volume of this series [21.