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Author: B. D. Carroll Publisher: ISBN: Category : Languages : en Pages : 25
Book Description
The research conducted on this project was concerned with the problem of test pattern generation for sequential logic circuits. More specifically, an algorithm was sought for generating test patterns for detecting single stuck-at faults in synchronous sequential circuits containing clocked flip-flop memory elements. In addition to the principal problem stated above, the related problems of test pattern generation for combinational iterative logic arrays and of test pattern generation for multiple faults in combinational logic circuits were also studied. A summary of the results obtained and the conclusions reached on the above problems is given. Suggestions for follow-on studies are discussed. Reprints of all papers published on the project are included in an appendix.
Author: B. D. Carroll Publisher: ISBN: Category : Languages : en Pages : 25
Book Description
The research conducted on this project was concerned with the problem of test pattern generation for sequential logic circuits. More specifically, an algorithm was sought for generating test patterns for detecting single stuck-at faults in synchronous sequential circuits containing clocked flip-flop memory elements. In addition to the principal problem stated above, the related problems of test pattern generation for combinational iterative logic arrays and of test pattern generation for multiple faults in combinational logic circuits were also studied. A summary of the results obtained and the conclusions reached on the above problems is given. Suggestions for follow-on studies are discussed. Reprints of all papers published on the project are included in an appendix.
Author: John Patrick Hayes Publisher: ISBN: Category : Electric networks Languages : en Pages : 272
Book Description
A network model, is introduced for the study of fault diagnosis in digital logic networks. It is shown that every network can be transformed into an equivalent normal NAND network from which all the information pertaining to the diagnosis of the original network can be obtained. The use of this model greatly simplifies fault analysis and test generation. The structure of the classes of indistinguishable faults in normal NAND networks is studied. It is shown that for certain types of networks, the indistinguishability classes can be characterized in a very simple manner. The conditions under which masking can occur are examined. These conditions lead to efficient methods for generating multiple-fault detection test sets. Some general bounds for the number of tests required by a network are examined. It is proven that for a n-input fanout-free network, the cardinality of any minimal detection or location test set lies between 2(square root of n) and 2n. It is argued that a 2-level realization of a random n-variable function requires, on the average, 2 to the (n-1) power tests to detect all faults. It is shown that for certain classes of functions there exists multi-level realizations which require relatively few tests, and for which complete detection test sets can easily be generated. (Author).
Author: Charles Wei-Yuan Cha Publisher: ISBN: Category : Languages : en Pages : 114
Book Description
A new concept, the prime fault, is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a functionally equivalent fault with prime faults as its only components. The use of prime faults greatly simplifies multiple fault analysis and test generation.
Author: B. D. Carroll
Author: B. D. Carroll
Author: Louis Gwo-Jiun Chu
Author: Heramb Singh
Author: Doctor Israel Koren
Author: John Patrick Hayes
Author: G. C. Jain
Author: Robert B. Sieffert
Author: 
Author: Charles Wei-Yuan Cha
Author: Herbert Y. Chang