A Structured ASIC Approach to a Radiation Hardened by Design Digital Single Sideband Modulator for Digital Radio Frequency Memories PDF Download
Are you looking for read ebook online? Search for your book and save it on your Kindle device, PC, phones or tablets. Download A Structured ASIC Approach to a Radiation Hardened by Design Digital Single Sideband Modulator for Digital Radio Frequency Memories PDF full book. Access full book title A Structured ASIC Approach to a Radiation Hardened by Design Digital Single Sideband Modulator for Digital Radio Frequency Memories by Thomas B. Pemberton. Download full books in PDF and EPUB format.
Author: Thomas B. Pemberton Publisher: ISBN: Category : Hilbert transform Languages : en Pages : 96
Book Description
Digital Radio Frequency Memories (DRFM) are widely used as modules in digital signal processing. These modules can provide several forms of signal manipulation and storage capabilities. With single event effects caused by environmental radiation the need for a radiation hardened DRFM is increased. Typical radiation hardening involves the use of specialized foundries utilizing proprietary CMOS libraries that are expensive to build or adding lead packages around a chip that is expensive and add weight to the chip. An alternative radiation hardening technique is to utilize a radiation hardened by design library. This library includes digital gates that have been hardened by the use of guard rings, reverse body bias or other methods. With the use of the hardened library, commercial synthesis tools can create a structural Verilog output from the behavioral VHDL design. The radiation hardened by design circuit will be larger than a non-hardened design, but can be fabricated using standard foundries. This research also takes advantage of current advancements of commercially available software and designs that have led to a structured ASIC approach for fabricating a design. This structured ASIC approach fabricates a design in two stages. The first stage is the transistor and bottom metal layers with the second stage being the top metal layers. Silicon wafers can be fabricated in bulk using the first stage of uncommitted logic with separate top metal layer masks applied to commit the logic to a specific design. A radiation hardened by design standard cell library was used to create the Structured ASIC standard cells and will allow production of radiation hardened circuits with a short design time. For this research, a generic frequency shifting DSSM is proposed that targets a radiation hardened by design Structured ASIC to deliver performance in processing as well as radiation hardening at both the transistor level and gate level. This research produces a parameterizable DSSM VHDL design that can be easily modified to produce a DSSM with various signal processing and storage capabilities with minimal modifications. The designed DSSM was tested on an FPGA board for prototyping, but was ultimately targeted for the radiation hardened by design structured ASIC. The design created through this research was compared to a non-hardened DSSM using a similar CMOS process for area, power, speed and Spur Free Dynamic Range.
Author: Thomas B. Pemberton Publisher: ISBN: Category : Hilbert transform Languages : en Pages : 96
Book Description
Digital Radio Frequency Memories (DRFM) are widely used as modules in digital signal processing. These modules can provide several forms of signal manipulation and storage capabilities. With single event effects caused by environmental radiation the need for a radiation hardened DRFM is increased. Typical radiation hardening involves the use of specialized foundries utilizing proprietary CMOS libraries that are expensive to build or adding lead packages around a chip that is expensive and add weight to the chip. An alternative radiation hardening technique is to utilize a radiation hardened by design library. This library includes digital gates that have been hardened by the use of guard rings, reverse body bias or other methods. With the use of the hardened library, commercial synthesis tools can create a structural Verilog output from the behavioral VHDL design. The radiation hardened by design circuit will be larger than a non-hardened design, but can be fabricated using standard foundries. This research also takes advantage of current advancements of commercially available software and designs that have led to a structured ASIC approach for fabricating a design. This structured ASIC approach fabricates a design in two stages. The first stage is the transistor and bottom metal layers with the second stage being the top metal layers. Silicon wafers can be fabricated in bulk using the first stage of uncommitted logic with separate top metal layer masks applied to commit the logic to a specific design. A radiation hardened by design standard cell library was used to create the Structured ASIC standard cells and will allow production of radiation hardened circuits with a short design time. For this research, a generic frequency shifting DSSM is proposed that targets a radiation hardened by design Structured ASIC to deliver performance in processing as well as radiation hardening at both the transistor level and gate level. This research produces a parameterizable DSSM VHDL design that can be easily modified to produce a DSSM with various signal processing and storage capabilities with minimal modifications. The designed DSSM was tested on an FPGA board for prototyping, but was ultimately targeted for the radiation hardened by design structured ASIC. The design created through this research was compared to a non-hardened DSSM using a similar CMOS process for area, power, speed and Spur Free Dynamic Range.
Author: Umberto Gatti Publisher: ISBN: 9788770224192 Category : Languages : en Pages :
Book Description
The book is intended for researchers and professionals interested in understanding how to design and make a preliminary characterization of Radiation Hardened (rad-hard) analog and mixed-signal circuits, exploiting standard CMOS manufacturing processes available from different silicon foundries and using different technology nodes. It starts with an introductory overview of the effects of radiation in space and harsh environments with a specific focus on analog circuits to enable the reader to understand why specific design solutions are adopted to mitigate hard/soft errors. The following four Chapters are devoted to RHBD (Radiation Hardening by Design) techniques for semiconductor components applied to Operational Amplifiers, Voltage References, Analog-to-Digital (ADC) and Digital-to-Analog (DAC) converters. Each Chapter is organized with a first part which recalls the basic working principles of such circuit and a second part which describes the main RHBD techniques proposed in the literature to make them resilient to radiation. The approach follows a top-down scheme starting from RHBD at circuit level (how to mitigate radiation effects by handling transistors in the proper way) and finishing at layout level (how to shape a layout to mitigate radiation effects). The last-but-one Chapter is devoted to a special class of analog circuit, the dosimeters, which are gaining importance in space, health and nuclear applications. By leveraging the characteristic of a Flash-memory cell, a re-usable dosimeter is described which includes the sensitive element itself, the analog interface and the process of characterization. The last part is an overview of the strategies adopted for the testing of analog and mixed-signal circuits. In particular, it will focus also on the measurement campaigns performed by the Authors aiming for the characterization of developed rad-hard components under total dose (TID) and single-events (SEE). Technical topics discussed in the book include: - Radiation effects on semiconductor components (TID, SEE) - Radiation Hardening by Design (RHBD) Techniques - Rad-hard Operational Amplifiers - Rad-hard Voltage References - Rad-hard ADC - Rad-hard DAC - Rad-hard Special Circuits - Testing Strategies
Author: Charu Nagpal Publisher: ISBN: Category : Languages : en Pages :
Book Description
With the relentless shrinking of the minimum feature size of VLSI Integrated Circuits (ICs), reduction in operating voltages and increase in operating frequencies, VLSI circuits are becoming more vulnerable to radiation strikes. As a result, this problem is now important not only for space and military electronics but also for consumer ICs. Thus, the design of radiation-hardened circuits has received significant attention in recent times. This thesis addresses the radiation hardening issue for VLSI ICs. In particular, circuit techniques are presented to protect against Single Event Transients (SETs). Radiation hardening has long been an area of research for memories for space and military ICs. In a memory, the stored state can ip as a result of a radiation strike. Such bit reversals in case of memories are known as Single Event Upsets (SEUs). With the feature sizes of VLSI ICs becoming smaller, radiation-induced glitches have become a source of concern in combinational circuits also. In combinational circuits, if a glitch due to a radiation event occurs at the time the circuit outputs are being sampled, it could lead to the propagation of a faulty value. The current or voltage glitches on the nodes of a combinational circuit are known as SETs. When an SET occurring on a node of a logic network is propagated through the gates of the network and is captured by a latch as a logic error, it is transformed to an SEU. The approach presented in this thesis makes use of Code Word State Preserving (CWSP) elements at each ip-op of the design, along with additional logic to trigger a recomputation in case a SET induced error is detected. The combinational part of the design is left unaltered. The CWSP element provides 100% SET protection for glitch widths up to min{(Dmin-D1)/2, (Dmax-D2)/2}, where Dmin and Dmax are the minimum and maximum circuit delay respectively. D1 and D2 are extra delays associated with the proposed SET protection circuit. The CWSP circuit has two inputs - the flip flop output signal and the same signal delayed by a quantity 6. In case an SET error is detected at the end of a clock period i, then the computation is repeated in clock period i+1, using the correct output value, which was captured by the CWSP element in the ith clock period. Unlike previous approaches, the CWSP element is i) in a secondary computational path and ii) the CWSP logic is designed to minimally impact the critical delay path of the design. It was found through SPICE simulations that the delay penalty of the proposed approach (averaged over several designs) is less than 1%. Thus, the proposed technique is applicable for high-speed designs, where the additional delay associated with the SET protection must be kept at a minimum.
Author: Jeffrey Prinzie Publisher: Springer ISBN: 9783030087456 Category : Technology & Engineering Languages : en Pages : 183
Book Description
This book presents state-of-the-art techniques for radiation hardened high-resolution Time-to-Digital converters and low noise frequency synthesizers. Throughout the book, advanced degradation mechanisms and error sources are discussed and several ways to prevent such errors are presented. An overview of the prerequisite physics of nuclear interactions is given that has been compiled in an easy to understand chapter. The book is structured in a way that different hardening techniques and solutions are supported by theory and experimental data with their various tradeoffs. Based on leading-edge research, conducted in collaboration between KU Leuven and CERN, the European Center for Nuclear Research Describes in detail advanced techniques to harden circuits against ionizing radiation Provides a practical way to learn and understand radiation effects in time-based circuits Includes an introduction to the underlying physics, circuit design, and advanced techniques accompanied with experimental data
Author: Srivatsan Chellappa Publisher: ISBN: Category : Electronic dissertations Languages : en Pages : 199
Book Description
Clock generation and distribution are essential to CMOS microchips, providing synchronization to external devices and between internal sequential logic. Clocks in microprocessors are highly vulnerable to single event effects and designing reliable energy efficient clock networks for mission critical applications is a major challenge. This dissertation studies the basics of radiation hardening, essentials of clock design and impact of particle strikes on clocks in detail and presents design techniques for hardening complete clock systems in digital ICs.Since the sequential elements play a key role in deciding the robustness of any clocking strategy, hardened-by-design implementations of triple-mode redundant (TMR) pulse clocked latches and physical design methodologies for using TMR master-slave flip-flops in application specific ICs (ASICs) are proposed. A novel temporal pulse clocked latch design for low power radiation hardened applications is also proposed. Techniques for designing custom RHBD clock distribution networks (clock spines) and ASIC clock trees for a radiation hardened microprocessor using standard CAD tools are presented. A framework for analyzing the vulnerabilities of clock trees in general, and study the parameters that contribute the most to the trees failure, including impact on controlled latches is provided. This is then used to design an integrated temporally redundant clock tree and pulse clocked flip-flop based clocking scheme that is robust to single event transients (SETs) and single event upsets (SEUs). Subsequently, designing robust clock delay lines for use in double data rate (DDRx) memory applications is studied in detail. Several modules of the proposed radiation hardened all-digital delay locked loop are designed and studied. Many of the circuits proposed in this entire body of work have been implemented and tested on a standard low-power 90-nm process.
Author: Chandarasekaran Ramamurthy Publisher: ISBN: Category : Electronic circuit design Languages : en Pages : 0
Book Description
Digital architectures for data encryption, processing, clock synthesis, data transfer, etc. are susceptible to radiation induced soft errors due to charge collection in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs). Radiation hardening by design (RHBD) techniques such as double modular redundancy (DMR) and triple modular redundancy (TMR) are used for error detection and correction respectively in such architectures. Multiple node charge collection (MNCC) causes domain crossing errors (DCE) which can render the redundancy ineffectual. This dissertation describes techniques to ensure DCE mitigation with statistical confidence for various designs. Both sequential and combinatorial logic are separated using these custom and computer aided design (CAD) methodologies. Radiation vulnerability and design overhead are studied on VLSI sub-systems including an advanced encryption standard (AES) which is DCE mitigated using module level coarse separation on a 90-nm process with 99.999% DCE mitigation. A radiation hardened microprocessor (HERMES2) is implemented in both 90-nm and 55-nm technologies with an interleaved separation methodology with 99.99% DCE mitigation while achieving 4.9% increased cell density, 28.5 % reduced routing and 5.6% reduced power dissipation over the module fences implementation. A DMR register-file (RF) is implemented in 55 nm process and used in the HERMES2 microprocessor. The RF array custom design and the decoders APR designed are explored with a focus on design cycle time. Quality of results (QOR) is studied from power, performance, area and reliability (PPAR) perspective to ascertain the improvement over other design techniques. A radiation hardened all-digital multiplying pulsed digital delay line (DDL) is designed for double data rate (DDR2/3) applications for data eye centering during high speed off-chip data transfer. The effect of noise, radiation particle strikes and statistical variation on the designed DDL are studied in detail. The design achieves the best in class 22.4 ps peak-to-peak jitter, 100-850 MHz range at 14 pJ/cycle energy consumption. Vulnerability of the non-hardened design is characterized and portions of the redundant DDL are separated in custom and auto-place and route (APR). Thus, a range of designs for mission critical applications are implemented using methodologies proposed in this work and their potential PPAR benefits explored in detail.
Author: Edvin Hjortland Publisher: ISBN: Category : Languages : en Pages : 294
Book Description
Two micro chips have been developed and implemented with a 0.18 um bulk based process technology. The first micro chip contains several NMOS transistors with different layout approaches. The chip includes standard gate, enclosed gate and H-shaped gate transistors, as well as different kinds of guard ring approaches. The fabricated chip will be tested to study the performance of the different layout approaches before and after irradiation.
Author: Grigorios Kalivas Publisher: John Wiley & Sons ISBN: 9780470748374 Category : Technology & Engineering Languages : en Pages : 472
Book Description
A systematic explanation of the principles of radio systems, Digital Radio System Design offers a balanced treatment of both digital transceiver modems and RF front-end subsystems and circuits. It provides an in-depth examination of the complete transceiver chain which helps to connect the two topics in a unified system concept. Although the book tackles such diverse fields it treats them in sufficient depth to give the designer a solid foundation and an implementation perspective. Covering the key concepts and factors that characterise and impact radio transmission and reception, the book presents topics such as receiver design, noise and distortion. Information is provided about more advanced aspects of system design such as implementation losses due to non-idealities. Providing vivid examples, illustrations and detailed case-studies, this book is an ideal introduction to digital radio systems design. Offers a balanced treatment of digital modem and RF front-end design concepts for complete transceivers Presents a diverse range of topics related to digital radio design including advanced transmission and synchronization techniques with emphasis on implementation Provides guidance on imperfections and non-idealities in radio system design Includes detailed design case-studies incorporating measurement and simulation results to illustrate the theory in practice
Author: Thomas B. Pemberton
Author: Thomas B. Pemberton
Author: Thomas A. Hopkins
Author: Thomas M. Foltz
Author: Umberto Gatti
Author: Charu Nagpal
Author: Jeffrey Prinzie
Author: Srivatsan Chellappa
Author: Chandarasekaran Ramamurthy
Author: Edvin Hjortland
Author: Grigorios Kalivas