Author: Eric David BoskinPublisher:
ISBN:
Category :
Languages : en
Pages : 312
Book Description
A Methodology for Modeling the Manufacturability of Integrated Circuits
Author: Eric David BoskinIntegrated Circuit Manufacturability
Author: José Pineda de GyvezPublisher: John Wiley & Sons
ISBN: 0780334477
Category : Technology & Engineering
Languages : en
Pages : 338
Book Description
"INTEGRATED CIRCUIT MANUFACTURABILITY provides comprehensive coverage of the process and design variables that determine the ease and feasibility of fabrication (or manufacturability) of contemporary VLSI systems and circuits. This book progresses from semiconductor processing to electrical design to system architecture. The material provides a theoretical background as well as case studies, examining the entire design for the manufacturing path from circuit to silicon. Each chapter includes tutorial and practical applications coverage. INTEGRATED CIRCUIT MANUFACTURABILITY illustrates the implications of manufacturability at every level of abstraction, including the effects of defects on the layout, their mapping to electrical faults, and the corresponding approaches to detect such faults. The reader will be introduced to key practical issues normally applied in industry and usually required by quality, product, and design engineering departments in today's design practices: * Yield management strategies * Effects of spot defects * Inductive fault analysis and testing * Fault-tolerant architectures and MCM testing strategies. This book will serve design and product engineers both from academia and industry. It can also be used as a reference or textbook for introductory graduate-level courses on manufacturing."
Design for Manufacturability and Statistical Design
Author: Michael OrshanskyPublisher: Springer Science & Business Media
ISBN: 0387690115
Category : Technology & Engineering
Languages : en
Pages : 319
Book Description
Design for Manufacturability and Statistical Design: A Comprehensive Approach presents a comprehensive overview of methods that need to be mastered in understanding state-of-the-art design for manufacturability and statistical design methodologies. Broadly, design for manufacturability is a set of techniques that attempt to fix the systematic sources of variability, such as those due to photolithography and CMP. Statistical design, on the other hand, deals with the random sources of variability. Both paradigms operate within a common framework, and their joint comprehensive treatment is one of the objectives of this book and an important differentation.
Predictive Modeling of Integrated Circuit Manufacturing Variation
Author: Swamy V. MudduPublisher:
ISBN:
Category :
Languages : en
Pages : 190
Book Description
Continuous scaling of feature sizes in CMOS integrated circuits (IC) pushes the design performance envelope as well as design complexity higher with each successive technology node. Advancements in materials and optics of the manufacturing process enable the scaling and manufacturability of devices in ICs. As device feature dimensions approach the physical limits of lithography and the manufacturing process, the smallest geometric and material variations manifest as design-level performance and power variability. One of the main pathological effects of IC scaling is the increase in design variability as a fraction of performance with each technology node. This design variability directly affects IC parametric (i.e., performance-limited) and catastrophic (i.e., defect-limited) yield, and consequently, IC cost. To address the increase in manufacturing variability in deep-submicron (DSM) technologies and to improve IC yield, a new design for manufacturability (DFM) paradigm has emerged in the recent past. The DFM paradigm encompasses a set of design methodologies that address manufacturing and process non-idealities at the design level to make ICs more robust to variations. DFM is also interpreted as a set of post-layout design fixing techniques that enhance and ease manufacturability. In general, the objective of DFM is to improve IC yield and cost by increasing manufacturing-awareness in the design phase, as well as design-awareness in the manufacturing phase. To achieve this dual objective of DFM, design must be driven by models of variation in the manufacturing process and the manufacturing process, must be made aware of the design intent. Variations in the IC manufacturing process are manifested as (1) deviation from the intended shapes of IC geometries, and (2) variations in impurity (i.e., dopant) concentrations. These variations are composed of systematic and random components. The systematic component of variation can be attributed to specific sources in the manufacturing process, while the random component is usually a result of confounding of several sources of variation and cannot be attributed to specific sources. A significant fraction of the total variation in shapes of IC geometries is systematic in sources such as focus, exposure dose, lens aberrations, etc. The objective of this thesis is to model the impact of the raw sources of variation at the mask making and wafer pattern transfer phases in manufacturing. The primary goal in the associated research is to develop models that can drive systematic variation-aware design. We propose techniques to model the impact of mask-level and wafer-level sources of variation on IC geometries. At the mask-level, proximity effects and resist heating caused by electron-beam writing are the two main sources of mask critical dimension (CD) errors. We propose a novel methodology to model resist heating caused by electron-beam writing on the mask resist. We use the resist heating model to drive temperature-aware mask writing schedules that minimize resist temperature, and consequently minimize mask CD error. Sub-wavelength optical lithography in sub-100nm technology nodes is enabled by resolution enhancement techniques (RETs) that allow patterning of layout features on silicon wafers. Optical proximity correction (OPC) is the most prominent RET used to compensate a design layout for optical and process effects prior to mask making and lithography. OPC modifies the shapes of layout features, and consequently increases mask complexity and cost. We develop a model of post-OPC mask cost of design features, to drive design-aware mask cost optimization. Despite advanced RETs and illumination techniques, several sources of variation in the pattern transfer process result in variations in chip-level performance and power. At 45nm and below, accurate design-level performance and power analyses must consider litho-simulated non-idealities in patterning. However, the simulation of exposure, resist and etch processing steps in lithography is computationally expensive to perform at chip-scale, and essentially infeasible during iterative design optimization. In this thesis, We develop a predictive model of post-OPC linewidth of devices in standard cells across the process window. The predictive model is fast, accurate and highly scalable, enabling its use in the design phase at full-chip scale without actually performing OPC and litho simulation. Last, we demonstrate the use of predictive linewidth models in fast and accurate leakage estimation and optimization. First, We discuss the use of through-focus systematic linewidth models to achieve accurate leakage estimation. We then discuss a novel detailed placement perturbation approach that leverages systematic pitch and focus interactions to improve leakage in light of systematic linewidth variation. These two methods demonstrate the use of predictive models of variation in driving variation-aware design analysis and optimization.
Nanoscale CMOS VLSI Circuits: Design for Manufacturability
Author: Sandip KunduPublisher: McGraw Hill Professional
ISBN: 0071635203
Category : Technology & Engineering
Languages : en
Pages : 316
Book Description
Cutting-Edge CMOS VLSI Design for Manufacturability Techniques This detailed guide offers proven methods for optimizing circuit designs to increase the yield, reliability, and manufacturability of products and mitigate defects and failure. Covering the latest devices, technologies, and processes, Nanoscale CMOS VLSI Circuits: Design for Manufacturability focuses on delivering higher performance and lower power consumption. Costs, constraints, and computational efficiencies are also discussed in the practical resource. Nanoscale CMOS VLSI Circuits covers: Current trends in CMOS VLSI design Semiconductor manufacturing technologies Photolithography Process and device variability: analyses and modeling Manufacturing-Aware Physical Design Closure Metrology, manufacturing defects, and defect extraction Defect impact modeling and yield improvement techniques Physical design and reliability DFM tools and methodologies
Fundamentals of Semiconductor Manufacturing and Process Control
Author: Gary S. MayPublisher: John Wiley & Sons
ISBN: 0471790273
Category : Technology & Engineering
Languages : en
Pages : 428
Book Description
A practical guide to semiconductor manufacturing from processcontrol to yield modeling and experimental design Fundamentals of Semiconductor Manufacturing and Process Controlcovers all issues involved in manufacturing microelectronic devicesand circuits, including fabrication sequences, process control,experimental design, process modeling, yield modeling, and CIM/CAMsystems. Readers are introduced to both the theory and practice ofall basic manufacturing concepts. Following an overview of manufacturing and technology, the textexplores process monitoring methods, including those that focus onproduct wafers and those that focus on the equipment used toproduce wafers. Next, the text sets forth some fundamentals ofstatistics and yield modeling, which set the foundation for adetailed discussion of how statistical process control is used toanalyze quality and improve yields. The discussion of statistical experimental design offers readers apowerful approach for systematically varying controllable processconditions and determining their impact on output parameters thatmeasure quality. The authors introduce process modeling concepts,including several advanced process control topics such asrun-by-run, supervisory control, and process and equipmentdiagnosis. Critical coverage includes the following: * Combines process control and semiconductor manufacturing * Unique treatment of system and software technology and managementof overall manufacturing systems * Chapters include case studies, sample problems, and suggestedexercises * Instructor support includes electronic copies of the figures andan instructor's manual Graduate-level students and industrial practitioners will benefitfrom the detailed exami?nation of how electronic materials andsupplies are converted into finished integrated circuits andelectronic products in a high-volume manufacturingenvironment. An Instructor's Manual presenting detailed solutions to all theproblems in the book is available from the Wiley editorialdepartment. An Instructor Support FTP site is also available.
Thermal and Power Management of Integrated Circuits
Author: Arman VassighiPublisher: Springer Science & Business Media
ISBN: 0387297499
Category : Technology & Engineering
Languages : en
Pages : 188
Book Description
In Thermal and Power Management of Integrated Circuits, power and thermal management issues in integrated circuits during normal operating conditions and stress operating conditions are addressed. Thermal management in VLSI circuits is becoming an integral part of the design, test, and manufacturing. Proper thermal management is the key to achieve high performance, quality and reliability. Performance and reliability of integrated circuits are strong functions of the junction temperature. A small increase in junction temperature may result in significant reduction in the device lifetime. This book reviews the significance of the junction temperature as a reliability measure under nominal and burn-in conditions. The latest research in the area of electro-thermal modeling of integrated circuits will also be presented. Recent models and associated CAD tools are covered and various techniques at the circuit and system levels are reviewed. Subsequently, the authors provide an insight into the concept of thermal runaway and how it may best be avoided. A section on low temperature operation of integrated circuits concludes the book.
Design for Manufacturability and Yield for Nano-Scale CMOS
Author: Charles ChiangPublisher: Springer Science & Business Media
ISBN: 1402051883
Category : Technology & Engineering
Languages : en
Pages : 277
Book Description
This book walks the reader through all the aspects of manufacturability and yield in a nano-CMOS process. It covers all CAD/CAE aspects of a SOC design flow and addresses a new topic (DFM/DFY) critical at 90 nm and beyond. This book is a must read book the serious practicing IC designer and an excellent primer for any graduate student intent on having a career in IC design or in EDA tool development.
Design for Manufacturability and Reliability Through Learning and Optimization
Author: Wei Ye (Ph. D.)Publisher:
ISBN:
Category :
Languages : en
Pages : 332
Book Description
Modern society relies on technologies with integrated circuits (ICs) at their heart. In the last several decades, as the performance and complexity of ICs keep escalating, the semiconductor industry has demonstrated an ability to develop new process techniques and product designs that are both manufacturable and reliable. However, as the transistor feature size is further shrunk into extreme scaling (e.g., 10 nm and beyond), large scale integration of transistors and interconnects brings ever-increasing challenges revolving around manufacturability and reliability. The major issues in manufacturability and reliability for modern ICs come from three aspects: (1) layout-dependent manufacturability (e.g., manufacturing yield sensitive to design patterns); (2) time-consuming process modeling (e.g., complex lithography systems); (3) design-sensitive reliability (e.g., lifetime related to layout designs). In order to close the gap between design and manufacturing and enhance design reliability, automated layout generation requires cross-layer information feed-forward and feedback, such as accurate process modeling and reliability-guided design optimization. This dissertation attempts to address the aforementioned challenges in manufacturing closure and reliability signoff through efficient machine learning techniques for lithography hotspot detection and lithography modeling, and synergistic design optimization for electromigration (EM). Our research includes efficient lithography hotspot detection, learning-based lithography modeling, and EM-aware physical design to achieve efficient manufacturing closure and reliability signoff. For lithography hotspot detection, due to the increasingly complicated design patterns, early and quick feedback for lithography hotspots is desired to guide design closure in early stages. Machine learning approaches have been successfully applied to hotspot detection while demonstrating a remarkable capability of generalization to unseen hotspot patterns. However, most of the proposed machine learning approaches are not yet able to answer two critical questions: model confidence and model efficiency. This study develops a lithography hotspot detection framework capable of providing modeling confidence with fewer training data and fewer expensive lithography simulations needed, and also provides a holistic measure for the intrinsic class imbalance in lithography hotspot detection. For lithography modeling, one of the major limitations in process modeling is considered: the trade-off between modeling efficiency and accuracy. The steady decrease of the feature sizes, along with the growing complexity and variation of the manufacturing process, has tremendously increased the lithography modeling complexity and prolonged the already-slow simulation procedure. Different modeling frameworks are proposed in this study, leveraging recent advancements in machine learning, particularly generative adversarial learning, to generate virtually simulated silicon image efficiently without running detailed optical simulations. With our proposed deep learning techniques, a significant improvement in modeling efficiency is achieved while maintaining high modeling accuracy. For EM-aware physical design, we demonstrate the limitation of conventional design and EM signoff flow when faced with the ever-growing EM violations in advanced technology nodes. Two essential directions are explored with practical algorithms and new design flows: (1) Power grid EM detection and optimization with several detailed placement techniques; (2) Learning-based signal EM prediction and mitigation at different physical design stages. The effectiveness of proposed design optimization and machine learning techniques is demonstrated with extensive experiments on industrial-strength benchmarks. Our approaches are capable of reducing turn-around time, saving modeling costs, and enabling fast manufacturing closure and reliability signoff
Process Variations and Probabilistic Integrated Circuit Design
Author: Manfred DietrichPublisher: Springer Science & Business Media
ISBN: 1441966218
Category : Technology & Engineering
Languages : en
Pages : 261
Book Description
Uncertainty in key parameters within a chip and between different chips in the deep sub micron area plays a more and more important role. As a result, manufacturing process spreads need to be considered during the design process. Quantitative methodology is needed to ensure faultless functionality, despite existing process variations within given bounds, during product development. This book presents the technological, physical, and mathematical fundamentals for a design paradigm shift, from a deterministic process to a probability-orientated design process for microelectronic circuits. Readers will learn to evaluate the different sources of variations in the design flow in order to establish different design variants, while applying appropriate methods and tools to evaluate and optimize their design.