A Hardware Analysis of the Fundamental Iterative Algorithm for Decoding a (17, 9) Binary BCH Code PDF Download

Author: Roy Lee Campbell
Publisher:
ISBN:
Category : Algorithms
Languages : en
Pages : 0

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ISBN:
Category :
Languages : en
Pages : 49

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The Berlekamp-Massey Algorithm (BMA) is commonly used in BCH decoding, but the Fundamental Iterative Algorithm (FIA) can, in many instances, correct more errors. The trade off lies in hardware complexity. The BMA has concise stages that do not require addressable memory, whereas the FIA struggles with memory management and complex stages. For the (17,9) BCH code over GF(256) with g(x)=m1(x), the FIA can correct up to two errors, but the BMA can correct only one error. Also, for a BER of 10( -5), the coding gains for the BMA and FIA are -.25dB and 1.4dB, respectively, which makes the FIA seem to be the better algorithm. The main drawback is the FIA is approximately 20 times more complex than the BMA. Also, the FIA does not have a critical path that is easily identified.

Author: Roy L. Campbell (Sr.)
Publisher:
ISBN:
Category : Algorithms
Languages : en
Pages : 0

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Author: Roy Lee Campbell
Publisher:
ISBN:
Category : Algorithms
Languages : en
Pages : 39

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Author:
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ISBN:
Category : Dissertations, Academic
Languages : en
Pages : 960

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Author: José Antonio Vanderhorst
Publisher:
ISBN:
Category : Binary system (Mathematics)
Languages : en
Pages : 150

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Author: Zhenshan Xie (Software engineer)
Publisher:
ISBN:
Category : Decoders (Electronics)
Languages : en
Pages : 0

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Generalized integrated interleaved (GII) codes are advanced error-correcting codes. They nest Reed-Solomon (RS) or BCH sub-codewords to generate more powerful RS or BCH codewords. The hyper-speed decoding and good error-correction capability make GII codes one of the best candidates for next-generation terabit/s digital storage and communications. However, the hardware architecture design for GII decoder faces many challenges. Above all, the key equation solving (KES) in the nested decoding stage causes clock frequency bottleneck and takes a large portion of the GII decoder area. Besides, short GII-BCH codes are required for new fast storage class memories (SCMs), which pose new issues for the GII-BCH decoder design. Many techniques have been developed in this dissertation to eliminate the implementation bottlenecks for almost every decoding step in the decoder architecture design, especially for the nested KES. Major contributions include: i) an efficient nested KES algorithm and architecture to eliminate the clock frequency bottleneck and substantially reduce the area complexity; ii) a scaled nested KES algorithm and architecture to further reduce the area complexity by scaling polynomials to enable product term sharing; iii) a fast nested KES algorithm and architecture to break data dependency to truly reduce the critical path to one multiplier and several adders/multiplexers and hence reduce the nested KES latency almost by half; iv) a scaled fast nested KES algorithm and architecture to further reduce the area complexity while keeping only one multiplier and several adders/multiplexers in the critical path; and v) a scheme to reduce the number of processing elements without undesirable degradation on the error-correcting performance. Compared to GII-RS decoding, the nested KES design for GII-BCH decoding is more challenging, since two instead of one higher-order syndromes need to be incorporated and every other iteration needs to be skipped. Efficient nested KES designs for GII-BCH codes have also been developed by algorithmic reformulations. For the overall GII decoder, the proposed designs can achieve more than 320Gb/s throughput with only 7 gates in the critical path. Several effective schemes have also been proposed to address the issues for applying GII-BCH codes to the new fast SCM applications, where short codes with low redundancy and high correction capability are required. In this case, the error correction capabilities of the sub- and nested codewords of the GII-BCH codes are relatively small, leading to issues regarding the KES throughput/latency and decoding miscorrections. i) A high-throughput sub-word KES was developed to directly compute the polynomials and variables for 3-error-correcting decoding. Utilizing the properties of the involved variables and syndromes, reformulations were developed to enable product term sharing and hence substantially simplify the polynomial and variable computation. Almost three times throughput with smaller area can be achieved, compared to the best previous design. ii) An efficient nested KES design has been proposed to eliminate the initialization clock from each nested decoding round. The polynomial updating was split and the critical path was reduced to one multiplier and several adders/multiplexers without pre-computing combined scalars. Substantial area saving can be achieved by sharing hardware units for polynomial updating. iii) Three low-complexity methods, i.e., checking nested syndromes, utilizing extended BCH codes, and tracking error locator polynomial degrees, have been proposed to detect and mitigate the miscorrections for the decoding of short GII-BCH codes, and hence the severe performance loss can be almost completely eliminated. iv) The miscorrection mitigation schemes were further optimized and the average nested decoding latency was reduced significantly. v) A sub-word selection strategy and a higher-order syndrome updating scheme were developed to reduce the worst-case nested decoding latency substantially. For an example short GII-BCH code over $GF(2^{10})$ for SCM applications, the performance gap due to miscorrections is closed and low-complexity and low-latency decoding is achieved. In summary, the proposed designs have significant contributions to the GII decoder architecture design, especially the nested KES, and the decoding of short GII-BCH codes. In the future study, the research focus can be on the joint architecture design for other decoder components, more efficient miscorrection mitigating schemes, and concise formulas for performance estimation.

Author: Rolf Johannesson
Publisher: John Wiley & Sons
ISBN: 1119098750
Category : Technology & Engineering
Languages : en
Pages : 550

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Fundamentals of Convolutional Coding, Second Edition, regarded as a bible of convolutional coding brings you a clear and comprehensive discussion of the basic principles of this field Two new chapters on low-density parity-check (LDPC) convolutional codes and iterative coding Viterbi, BCJR, BEAST, list, and sequential decoding of convolutional codes Distance properties of convolutional codes Includes a downloadable solutions manual

Author: Frédéric Fontaine (Michel)
Publisher:
ISBN:
Category :
Languages : en
Pages : 242

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Author: Anuradha A. Gautam
Publisher:
ISBN:
Category :
Languages : en
Pages : 250

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Book Description
Data corruption during the transmission and reception of data because of noisy channel medium is the most common problem faced in digital communication system. Thus, it is hard to get the reliable communication. Thus, to get the error free communication, we need Error correction code. BCH codes is an acronym for Bose, Ray -- Chaudhuri, Hocquenghem, invented in 1960s and today they are used as a baseline for many recent Error Correcting Codes. BCH codes are powerful class of multiple error correction codes with well defined mathematical properties. BCH code is used to correct multiple random error patterns. The mathematical properties within which BCH codes are defined are the Galois Field or Finite Field Theory. The main focus of this project is to design encoder and decoder architecture for BCH codes. The design of an encoder is based on Liner Feed Back Shift Register used for polynomial division and the decoder design is based on ibm algorithm to correct the errors occurred during transmission. Also this project report contains comparison of BCH codes with other Error Correcting codes and gives the detailed explanation of salient feature of BCH codes. The combination of BCH codes and LDPC codes are used for error correction for satellite communication standards. The BCH codes architecture is described using hardware description language called Verilog and synthesized using Xilinx Webpack 10.1 ISE. The performance of the whole model is check in terms of simulation using Xilinx Modelsim.